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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id b22-20020a170906039600b009b2b53c4463si2416241eja.196.2023.10.07.00.05.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Oct 2023 00:05:49 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9B68B385C6E6 for ; Sat, 7 Oct 2023 07:05:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 2F8633858426 for ; Sat, 7 Oct 2023 07:05:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2F8633858426 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp87t1696662300tcl5gdqk Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 07 Oct 2023 15:04:58 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: q+EIYT+FhZpZGpReQ14R/zTgT8mLqJ7++DN3bpRg9wZ7kdNdxpKUwOa3+Inyc z5+ODNozFooRZ9rW8TTagzq1JW3kW+yBb/GFeD3DxkZ3xJ5nagpTVeH+IlXpPw83/NtIBVv 6ry9QWJz+GfbPHTkyO93gXFH/RnW6TdIsn4OsAxw9CLR0d3Rr/iVqUfCmRi56XNYsIOm01M zVrIpVE8gpIqKzLMyfHpJXvY8c57Lxew5r52j+RDkASuiXSjIFMv6saTZKzyl1bkUV4FBSB rfrNoherl2OYncQtRMVql/F/MQKUrc9jfs3ZmhG2Vkn0YNY5mXSoJsZgNF0FwoZqfvPKfTF OeOP3CIV5uo2VU/miEuYlQkghEWA5Pw+DsYuVKG66avXoztHPsDTfJ8q9FFiw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12123880656890955107 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Enable more tests of "vect" for RVV Date: Sat, 7 Oct 2023 15:04:58 +0800 Message-Id: <20231007070458.460506-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779079420079538551 X-GMAIL-MSGID: 1779079420079538551 This patch enables almost full coverage vectorization tests for RVV, except these following tests (not enabled yet): 1. Will enable soon: check_effective_target_vect_call_lrint check_effective_target_vect_call_btrunc check_effective_target_vect_call_btruncf check_effective_target_vect_call_ceil check_effective_target_vect_call_ceilf check_effective_target_vect_call_floor check_effective_target_vect_call_floorf check_effective_target_vect_call_lceil check_effective_target_vect_call_lfloor check_effective_target_vect_call_nearbyint check_effective_target_vect_call_nearbyintf check_effective_target_vect_call_round check_effective_target_vect_call_roundf 2. Not sure we will need to enable or not: check_effective_target_vect_complex_* check_effective_target_vect_simd_clones check_effective_target_vect_bswap check_effective_target_vect_widen_shift check_effective_target_vect_widen_mult_* check_effective_target_vect_widen_sum_* check_effective_target_vect_unpack check_effective_target_vect_interleave check_effective_target_vect_extract_even_odd check_effective_target_vect_pack_trunc check_effective_target_vect_check_ptrs check_effective_target_vect_sdiv_pow2_si check_effective_target_vect_usad_* check_effective_target_vect_udot_* check_effective_target_vect_sdot_* check_effective_target_vect_gather_load_ifn After this patch, we will have these following additional FAILs: XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1115.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1115.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s114.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s114.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1161.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1161.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1232.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1232.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s124.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s124.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1279.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1279.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s161.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s161.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s253.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s253.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s257.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s257.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s271.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s271.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2711.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2711.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2712.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s2712.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s272.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s272.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s273.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s273.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s274.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s274.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s276.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s276.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s278.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s278.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s279.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s279.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s3111.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s3111.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s353.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s353.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s441.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s441.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s443.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s443.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-vif.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-vif.c scan-tree-dump vect "vectorized 1 loops" FAIL: gcc.dg/vect/vect-114.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorized 0 loops" 1 FAIL: gcc.dg/vect/vect-114.c scan-tree-dump-times vect "vectorized 0 loops" 1 FAIL: gcc.dg/vect/vect-live-2.c -flto -ffat-lto-objects scan-tree-dump-times vect "vec_stmt_relevant_p: stmt live but not relevant" 1 FAIL: gcc.dg/vect/vect-live-2.c scan-tree-dump-times vect "vec_stmt_relevant_p: stmt live but not relevant" 1 FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects scan-tree-dump vect "Reduce using vector shifts" FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using vector shifts" FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects scan-tree-dump vect "Reduce using vector shifts" FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using vector shifts" FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_ADD" FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_SUB" FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_MUL" FAIL: gcc.dg/vect/vect-cond-arith-5.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_RDIV" They are all dump FAILs (No more ICE and execution FAILs). Fixing those FAILs will be another separate patch. But I think we should commit this patch first. Ok for trunk ? gcc/testsuite/ChangeLog: * lib/target-supports.exp: Enable more vect tests for RVV. --- gcc/testsuite/lib/target-supports.exp | 138 +++++++++++++++++++------- 1 file changed, 101 insertions(+), 37 deletions(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 64889fa6d34..596134fa2b1 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3970,7 +3970,8 @@ proc check_effective_target_vect_int { } { || [et-is-effective-target mips_msa])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget riscv*-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } @@ -4098,7 +4099,9 @@ proc check_effective_target_vect_intfloat_cvt { } { && [et-is-effective-target mips_msa]) || [istarget amdgcn-*-*] || ([istarget s390*-*-*] - && [check_effective_target_s390_vxe2]) }}] + && [check_effective_target_s390_vxe2]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports signed double->int conversion @@ -4117,7 +4120,9 @@ proc check_effective_target_vect_doubleint_cvt { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] - && [check_effective_target_s390_vx]) }}] + && [check_effective_target_s390_vx]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports signed int->double conversion @@ -4136,7 +4141,9 @@ proc check_effective_target_vect_intdouble_cvt { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] - && [check_effective_target_s390_vx]) }}] + && [check_effective_target_s390_vx]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } #Return 1 if we're supporting __int128 for target, 0 otherwise. @@ -4167,7 +4174,9 @@ proc check_effective_target_vect_uintfloat_cvt { } { && [et-is-effective-target mips_msa]) || [istarget amdgcn-*-*] || ([istarget s390*-*-*] - && [check_effective_target_s390_vxe2]) }}] + && [check_effective_target_s390_vxe2]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } @@ -4184,7 +4193,9 @@ proc check_effective_target_vect_floatint_cvt { } { && [et-is-effective-target mips_msa]) || [istarget amdgcn-*-*] || ([istarget s390*-*-*] - && [check_effective_target_s390_vxe2]) }}] + && [check_effective_target_s390_vxe2]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports unsigned float->int conversion @@ -4199,7 +4210,9 @@ proc check_effective_target_vect_floatuint_cvt { } { && [et-is-effective-target mips_msa]) || [istarget amdgcn-*-*] || ([istarget s390*-*-*] - && [check_effective_target_s390_vxe2]) }}] + && [check_effective_target_s390_vxe2]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if peeling for alignment might be profitable on the target @@ -7275,7 +7288,9 @@ proc check_effective_target_vect_shift { } { || [et-is-effective-target mips_loongson_mmi])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports hardware vector shift by register operation. @@ -7285,6 +7300,8 @@ proc check_effective_target_vect_var_shift { } { expr {(([istarget i?86-*-*] || [istarget x86_64-*-*]) && [check_avx2_available]) || [istarget aarch64*-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } @@ -7299,7 +7316,9 @@ proc check_effective_target_whole_vector_shift { } { && [et-is-effective-target mips_loongson_mmi]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] } { + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) } { set answer 1 } else { set answer 0 @@ -7327,7 +7346,9 @@ proc check_effective_target_vect_bool_cmp { } { return [check_cached_effective_target_indexed vect_bool_cmp { expr { [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget aarch64*-*-*] - || [is-effective-target arm_neon] }}] + || [is-effective-target arm_neon] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports addition of char vectors for at least @@ -7348,6 +7369,8 @@ proc check_effective_target_vect_char_add { } { || [et-is-effective-target mips_msa])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } @@ -7362,7 +7385,9 @@ proc check_effective_target_vect_shift_char { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports hardware vectors of long, 0 otherwise. @@ -7381,7 +7406,9 @@ proc check_effective_target_vect_long { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] } { + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) } { set answer 1 } else { set answer 0 @@ -7409,7 +7436,9 @@ proc check_effective_target_vect_float { } { || [is-effective-target arm_neon] || ([istarget s390*-*-*] && [check_effective_target_s390_vxe]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports hardware vectors of float without @@ -7438,7 +7467,9 @@ proc check_effective_target_vect_double { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*]} }] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v])} }] } # Return 1 if the target supports conditional addition, subtraction, @@ -7446,7 +7477,8 @@ proc check_effective_target_vect_double { } { # via the cond_ optabs. Return 0 otherwise. proc check_effective_target_vect_double_cond_arith { } { - return [check_effective_target_aarch64_sve] + return [expr { [check_effective_target_aarch64_sve] + || [check_effective_target_riscv_v] }] } # Return 1 if the target supports hardware vectors of long long, 0 otherwise. @@ -7463,7 +7495,9 @@ proc check_effective_target_vect_long_long { } { || ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*] && [check_effective_target_has_arch_pwr8]) - || [istarget aarch64*-*-*] }}] + || [istarget aarch64*-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v])}}] } @@ -7516,7 +7550,9 @@ proc check_effective_target_vect_perm { } { || [et-is-effective-target mips_msa])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if, for some VF: @@ -7609,7 +7645,9 @@ proc check_effective_target_vect_perm_byte { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports SLP permutation of 3 vectors when each @@ -7638,7 +7676,9 @@ proc check_effective_target_vect_perm_short { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports SLP permutation of 3 vectors when each @@ -7903,8 +7943,10 @@ proc check_effective_target_vect_usad_char { } { # and unsigned average operations on vectors of bytes. proc check_effective_target_vect_avg_qi {} { - return [expr { [istarget aarch64*-*-*] - && ![check_effective_target_aarch64_sve1_only] }] + return [expr { ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve1_only]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }] } # Return 1 if the target plus current options supports both signed @@ -8595,7 +8637,8 @@ proc check_effective_target_vect_load_lanes { } { proc check_effective_target_vect_masked_load { } { return [expr { [check_avx_available] || [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] } ] + || [istarget amdgcn*-*-*] + || [check_effective_target_riscv_v] } ] } # Return 1 if the target supports vector masked stores. @@ -8617,7 +8660,8 @@ proc check_effective_target_vect_gather_load_ifn { } { proc check_effective_target_vect_scatter_store { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] }] + || [istarget amdgcn*-*-*] + || [check_effective_target_riscv_v] }] } # Return 1 if the target supports vector conditional operations, 0 otherwise. @@ -8634,7 +8678,9 @@ proc check_effective_target_vect_condition { } { && [check_effective_target_arm_neon_ok]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports vector conditional operations where @@ -8651,7 +8697,9 @@ proc check_effective_target_vect_cond_mixed { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports vector char multiplication, 0 otherwise. @@ -8667,7 +8715,9 @@ proc check_effective_target_vect_char_mult { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports vector short multiplication, 0 otherwise. @@ -8685,7 +8735,8 @@ proc check_effective_target_vect_short_mult { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] - || [istarget riscv*-*-*] }}] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports vector int multiplication, 0 otherwise. @@ -8702,7 +8753,8 @@ proc check_effective_target_vect_int_mult { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] - || [istarget riscv*-*-*] }}] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports 64 bit hardware vector @@ -8719,7 +8771,9 @@ proc check_effective_target_vect_long_mult { } { || ([istarget sparc*-*-*] && [check_effective_target_ilp32]) || [istarget aarch64*-*-*] || ([istarget mips*-*-*] - && [et-is-effective-target mips_msa]) } { + && [et-is-effective-target mips_msa]) + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) } { set answer 1 } else { set answer 0 @@ -8735,7 +8789,9 @@ proc check_effective_target_vect_int_mod { } { return [check_cached_effective_target_indexed vect_int_mod { expr { ([istarget powerpc*-*-*] && [check_effective_target_has_arch_pwr10]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports vector even/odd elements extraction, 0 otherwise. @@ -8825,7 +8881,7 @@ proc available_vector_sizes { } { lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2 } elseif { [istarget riscv*-*-*] } { if { [check_effective_target_riscv_v] } { - lappend result 0 32 + lappend result 0 32 64 128 } lappend result 128 } else { @@ -8884,7 +8940,9 @@ proc check_effective_target_vect_call_copysignf { } { expr { [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget powerpc*-*-*] || [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports hardware square root instructions. @@ -8921,7 +8979,9 @@ proc check_effective_target_vect_call_sqrtf { } { || ([istarget powerpc*-*-*] && [check_vsx_hw_available]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || ([istarget riscv*-*-*] + && [check_effective_target_riscv_v]) }}] } # Return 1 if the target supports vector lrint calls. @@ -9032,14 +9092,16 @@ proc check_effective_target_vect_call_roundf { } { proc check_effective_target_vect_logical_reduc { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn-*-*] }] + || [istarget amdgcn-*-*] + || [check_effective_target_riscv_v] }] } # Return 1 if the target supports the fold_extract_last optab. proc check_effective_target_vect_fold_extract_last { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] }] + || [istarget amdgcn*-*-*] + || [check_effective_target_riscv_v] }] } # Return 1 if the target supports section-anchors @@ -9932,7 +9994,8 @@ proc check_effective_target_vect_sizes_32B_16B { } { proc check_effective_target_vect_sizes_16B_8B { } { if { [check_avx_available] || [is-effective-target arm_neon] - || [istarget aarch64*-*-*] } { + || [istarget aarch64*-*-*] + || [check_effective_target_riscv_v] } { return 1; } else { return 0; @@ -11874,7 +11937,8 @@ proc check_effective_target_builtin_eh_return { } { # Return 1 if the target supports max reduction for vectors. proc check_effective_target_vect_max_reduc { } { - if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] } { + if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] + || [check_effective_target_riscv_v] } { return 1 } return 0