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[8.43.85.97]) by mx.google.com with ESMTPS id y12-20020a17090614cc00b009b95012a678si2266201ejc.381.2023.10.06.23.37.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 23:37:33 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dzcqXIbE; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 19D8A385C301 for ; Sat, 7 Oct 2023 06:37:21 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id AFA073857020 for ; Sat, 7 Oct 2023 06:36:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AFA073857020 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696660616; x=1728196616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mU55EvuBTTe6X0WcG6VM857JL2thQ956fEGOpqDWVDM=; b=dzcqXIbEso/0mFEsNkPmqvLkmsdDRlFSesWseE6n2BnVxogcehVj29QB v5bO4M1BDZFrjHnfdHN4hsEUuRbfc7MY9Lmb3trszI0icTC3bD8+oHkR+ AGacegZ+zls2y20oX9EZ1Pn/ilwob0LMLy8dSum90PZDTM6CJW+6NCGYw Cj1SawwFwL1ICFTGlBN0Ey881kYlhh5eMI4qagLI1nVyxYyThlaZnlpF/ cwQyxxFjhRwGNTYlTfgMlwYUcpBmRLg5MWt3Mj6+MCPM/4VqHv8Mw8KCw V0dpCEHI/+T8JtOiSK35yOMGvQxgIVcTs2TND+9xptK1y9poMiZqlE/Z8 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="414894564" X-IronPort-AV: E=Sophos;i="6.03,205,1694761200"; d="scan'208";a="414894564" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 23:36:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="822763234" X-IronPort-AV: E=Sophos;i="6.03,205,1694761200"; d="scan'208";a="822763234" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 06 Oct 2023 23:36:53 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5931C100566E; Sat, 7 Oct 2023 14:36:52 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, zingaburga@hotmail.com Subject: [PATCH v2 01/18] Initial support for -mevex512 Date: Sat, 7 Oct 2023 14:34:52 +0800 Message-Id: <20231007063452.3605029-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230921072013.2124750-2-lin1.hu@intel.com> References: <20230921072013.2124750-2-lin1.hu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777631022824625892 X-GMAIL-MSGID: 1779077641390432402 Hi all, Sorry for the patch revision delay since just back from the vacation. I have slightly revised this patch for the __EVEX256__ request with the code: diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 47768fa0940..9c44bd7fb63 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -546,7 +546,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, if (isa_flag & OPTION_MASK_ISA_AVX512BW) def_or_undef (parse_in, "__AVX512BW__"); if (isa_flag & OPTION_MASK_ISA_AVX512VL) - def_or_undef (parse_in, "__AVX512VL__"); + { + def_or_undef (parse_in, "__AVX512VL__"); + def_or_undef (parse_in, "__EVEX256__"); + } if (isa_flag & OPTION_MASK_ISA_AVX512VBMI) def_or_undef (parse_in, "__AVX512VBMI__"); if (isa_flag & OPTION_MASK_ISA_AVX512IFMA) See if it meets the need. If there is no concern, I will commit all 18 patches on Monday or Tuesday. Thx, Haochen gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_EVEX512_SET): New. (OPTION_MASK_ISA2_EVEX512_UNSET): Ditto. (ix86_handle_option): Handle EVEX512. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle EVEX512. Add __EVEX256__ when AVX512VL is set. * config/i386/i386-options.cc: (isa2_opts): Handle EVEX512. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_option_override_internal): Set EVEX512 target if it is not explicitly set when AVX512 is enabled. Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. * config/i386/i386.opt: Add mevex512. Temporaily RejectNegative. --- gcc/common/config/i386/i386-common.cc | 15 +++++++++++++++ gcc/config/i386/i386-c.cc | 7 ++++++- gcc/config/i386/i386-options.cc | 19 ++++++++++++++++++- gcc/config/i386/i386.opt | 4 ++++ 4 files changed, 43 insertions(+), 2 deletions(-) diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 95468b7c405..8cc59e08d06 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -123,6 +123,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3 #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512 #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4 +#define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -309,6 +310,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3 #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512 #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4 +#define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -1341,6 +1343,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mevex512: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 47768fa0940..9c44bd7fb63 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -546,7 +546,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, if (isa_flag & OPTION_MASK_ISA_AVX512BW) def_or_undef (parse_in, "__AVX512BW__"); if (isa_flag & OPTION_MASK_ISA_AVX512VL) - def_or_undef (parse_in, "__AVX512VL__"); + { + def_or_undef (parse_in, "__AVX512VL__"); + def_or_undef (parse_in, "__EVEX256__"); + } if (isa_flag & OPTION_MASK_ISA_AVX512VBMI) def_or_undef (parse_in, "__AVX512VBMI__"); if (isa_flag & OPTION_MASK_ISA_AVX512IFMA) @@ -707,6 +710,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__SHA512__"); if (isa_flag2 & OPTION_MASK_ISA2_SM4) def_or_undef (parse_in, "__SM4__"); + if (isa_flag2 & OPTION_MASK_ISA2_EVEX512) + def_or_undef (parse_in, "__EVEX512__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index e47f9ed5d5f..a1a7a92da9f 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -250,7 +250,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 }, { "-msm3", OPTION_MASK_ISA2_SM3 }, { "-msha512", OPTION_MASK_ISA2_SHA512 }, - { "-msm4", OPTION_MASK_ISA2_SM4 } + { "-msm4", OPTION_MASK_ISA2_SM4 }, + { "-mevex512", OPTION_MASK_ISA2_EVEX512 } }; static struct ix86_target_opts isa_opts[] = { @@ -1109,6 +1110,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("sm3", OPT_msm3), IX86_ATTR_ISA ("sha512", OPT_msha512), IX86_ATTR_ISA ("sm4", OPT_msm4), + IX86_ATTR_ISA ("evex512", OPT_mevex512), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), @@ -2559,6 +2561,21 @@ ix86_option_override_internal (bool main_args_p, &= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM) & ~opts->x_ix86_isa_flags_explicit); + /* Set EVEX512 target if it is not explicitly set + when AVX512 is enabled. */ + if (TARGET_AVX512F_P(opts->x_ix86_isa_flags) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512; + + /* Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. */ + if (!TARGET_EVEX512_P(opts->x_ix86_isa_flags2)) + { + opts->x_ix86_isa_flags + &= ~(OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512ER); + opts->x_ix86_isa_flags2 + &= ~(OPTION_MASK_ISA2_AVX5124FMAPS | OPTION_MASK_ISA2_AVX5124VNNIW); + } + /* Validate -mpreferred-stack-boundary= value or default it to PREFERRED_STACK_BOUNDARY_DEFAULT. */ ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT; diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 78b499304a4..6d8601b1f75 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1310,3 +1310,7 @@ Enable vectorization for gather instruction. mscatter Target Alias(mtune-ctrl=, use_scatter, ^use_scatter) Enable vectorization for scatter instruction. + +mevex512 +Target RejectNegative Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save +Support 512 bit vector built-in functions and code generation.