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[98.210.197.24]) by smtp.gmail.com with ESMTPSA id x20-20020a62fb14000000b006889081281bsm1784293pfm.138.2023.10.06.11.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 11:22:57 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Jeff Law , Palmer Dabbelt , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [COMMITTED] RISC-V: const: hide mvconst splitter from IRA Date: Fri, 6 Oct 2023 11:22:50 -0700 Message-Id: <20231006182250.393162-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779031457673948972 X-GMAIL-MSGID: 1779031457673948972 Vlad recently introduced a new gate @ira_in_progress, similar to counterparts @{reload,lra}_in_progress. Use this to hide the constant synthesis splitter from being recog* () by IRA register equivalence logic which is eager to undo the splits, generating worse code for constants (and sometimes no code at all). See PR/109279 (large constant), PR/110748 (const -0.0) ... Granted the IRA logic is subsided with -fsched-pressure which is now enabled for RISC-V backend, the gate makes this future-proof in addition to helping with -O1 etc. This fixes 1 addition test ========= Summary of gcc testsuite ========= | # of unexpected case / # of unique unexpected case | gcc | g++ | gfortran | rv32imac/ ilp32/ medlow | 416 / 103 | 13 / 6 | 67 / 12 | rv32imafdc/ ilp32d/ medlow | 416 / 103 | 13 / 6 | 24 / 4 | rv64imac/ lp64/ medlow | 417 / 104 | 9 / 3 | 67 / 12 | rv64imafdc/ lp64d/ medlow | 416 / 103 | 5 / 2 | 6 / 1 | Also similar to v1, this doesn't move RISC-V SPEC scores at all. gcc/ChangeLog: * config/riscv/riscv.md (mvconst_internal): Add !ira_in_progress. Suggested-by: Jeff Law Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv.md | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1ebe8f92284d..da84b9357bd3 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1997,13 +1997,16 @@ ;; Pretend to have the ability to load complex const_int in order to get ;; better code generation around them. -;; ;; But avoid constants that are special cased elsewhere. +;; +;; Hide it from IRA register equiv recog* () to elide potential undoing of split +;; (define_insn_and_split "*mvconst_internal" [(set (match_operand:GPR 0 "register_operand" "=r") (match_operand:GPR 1 "splittable_const_int_operand" "i"))] - "!(p2m1_shift_operand (operands[1], mode) - || high_mask_shift_operand (operands[1], mode))" + "!ira_in_progress + && !(p2m1_shift_operand (operands[1], mode) + || high_mask_shift_operand (operands[1], mode))" "#" "&& 1" [(const_int 0)]