From patchwork Fri Oct 6 11:55:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 149209 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:403:3b70:6f57 with SMTP id x8csp264964vqo; Fri, 6 Oct 2023 04:58:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEoBJX9ma88+GDGl0W4kAIyWggN4NZzNSEv/SK+UpR2+25Fs8bexAGwiRr/mZf22md+qBRp X-Received: by 2002:aa7:d314:0:b0:530:c0ac:8ca1 with SMTP id p20-20020aa7d314000000b00530c0ac8ca1mr6186789edq.42.1696593499678; Fri, 06 Oct 2023 04:58:19 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696593499; cv=pass; d=google.com; s=arc-20160816; b=HttGyLj0Sc2y/d1yyH6xhl7YLRNMjj81M4DX/Mqf06S6+cHysKh6FtbQyIzO1Bi4Xu 3QotElo68A4ECFHmmWAdx5XKZO2YbV9TRig1W0mZEnJj8ov9z8sK8RT69kv6CVW/m0sy Lj/kXhlDjk+gYtJQ03WFDEiudULNybWOwgiNHFX1PfFYWLRFsANTsJlABYGnOrfbmAkN eDKwasuLpphsp35CfMXJKdTFnnseDMzDe1eh6qnpXzTSCPNplDz8DsEgxP1A0KTfyix6 QpFKrHPLq0YAdhXLTpg+2mVicdLs2+04Os2/5s/45MUmSfxHSogdbvK5Jo5+zplmWBFr M4mg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:nodisclaimer :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :dmarc-filter:delivered-to; bh=1B2jlTzmkdge69WxB/YBZXqiM9kZOcT+fw5A5NNfm4g=; fh=cdLUSjbFO0/cTi+z3xcckFOOtvTDyNZWtn2WcodW9fw=; b=Urv4LLJ1mjHmIUBfBSGaUOavedW/1ZLGs7Sdd51s2jJ2mm2JwcKxUuPf07894EVpQp qvdagodKENJOQjOIZHknr5vceq1tGEiCQvNgIl8jhc/hn8wGQhebNL1cUYC04NYe8Uy1 pr5HVEbDnS7GbefGsuy/09jFyQdABkAEAndwL6blIAok8y0xEGCXx+Rw4yw7e/9elbVq 350nEGE1dRH3Slx/Wa/Lym1VSsSIOk80/X9O1aF2kMva2S8QFTm7AX0Mvn1GCkOkRvjs HlgSOV7jPwBwM+AJFmp5wBbRbrgC9OOT+H/pRkqDDV2Hgj610dilHeWjvwClaUGVfKiM /ETg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=9wjzpajk; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=9wjzpajk; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q11-20020a056402032b00b00536b154c634si1541444edw.260.2023.10.06.04.58.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 04:58:19 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=9wjzpajk; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=9wjzpajk; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 386923831E13 for ; Fri, 6 Oct 2023 11:56:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2048.outbound.protection.outlook.com [40.107.20.48]) by sourceware.org (Postfix) with ESMTPS id E4B303857C66 for ; Fri, 6 Oct 2023 11:56:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E4B303857C66 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1B2jlTzmkdge69WxB/YBZXqiM9kZOcT+fw5A5NNfm4g=; b=9wjzpajksEV08L3wFHPVhcdqtsmSw5DyFJ65LG4dPdIi3Qn05aLuCWaI51hBmueTSCTaVpCDUNdGQ7IEckeAPA+BeorgbBmZiVs0gJT1T+/c0XS5nqrouOznk5E94RQibYQQ8Ch/iV06uSvhqUE8f8YBUH91rUm+79udtoOaOEM= Received: from DU6P191CA0053.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:53e::23) by DB9PR08MB6538.eurprd08.prod.outlook.com (2603:10a6:10:23d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.37; Fri, 6 Oct 2023 11:56:23 +0000 Received: from DBAEUR03FT056.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:53e:cafe::d3) by DU6P191CA0053.outlook.office365.com (2603:10a6:10:53e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.37 via Frontend Transport; Fri, 6 Oct 2023 11:56:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT056.mail.protection.outlook.com (100.127.142.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.26 via Frontend Transport; Fri, 6 Oct 2023 11:56:23 +0000 Received: ("Tessian outbound ab4fc72d2cd4:v211"); Fri, 06 Oct 2023 11:56:23 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 9b5f07425951db04 X-CR-MTA-TID: 64aa7808 Received: from e29742ab7859.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 01C0A432-EC2E-4FF7-B906-0A37F1ED1B58.1; Fri, 06 Oct 2023 11:56:17 +0000 Received: from EUR03-AM7-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id e29742ab7859.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 06 Oct 2023 11:56:17 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=O9moYNkykKPAFsOwb/RpZk3I7sX5rWmQi1RMl+b5w2TL4W9f0TjBC6kp7SsIS+uPPYphVRGNHIjuSBiX9NQqm0wHcjHXW0fpJFi3IUfAC0muclR7h20YvdSKz6/faN01qFxma6oe+i2CA487Ruz6xPt3p2Qxtr3AVEN7tuS8ueVe544AhdgcrB9j3Lp99cu3oWvrYl0P3bpN8zxLnwOvTPK/V0bj4esaR0bfnL8q+QUDjz4u/lArYPK7Ykpy9qZtWKIHCmMNyOr042t6ZrVR8jMYMiJqCW2jG/KmDcV2y+HEDrYO1trXy3m7Ijp0Rvxfxe10mUjpTQ//SXEstx5R8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1B2jlTzmkdge69WxB/YBZXqiM9kZOcT+fw5A5NNfm4g=; b=nSyG28VhCw2eEk60JxXh7y+Z2iwTZCyNjnctS5N0+9UbjnFIrvPgOaQgbphQFORhI1HHEFralHTr7dUvoC0vxZh5U+tQkcNCGjm2zLkxFWFXCjSLMd0P6MHy8nVa6tjss7/SidY1XRQgCS9+HCasY3e9JEbQQzI0PkN4Zc14qNbyY+fHBHfDdmoeNqWUzRnUGxyogByADJJR/9qhI45W+eaIW4twgOfGxr0qLd/WKQnawvDpb24N6BW+cXU7PFfpaw2dr5dD60VhOeugqm3QhK2CIXDDQGVg08+JrKwlAs8XHnIvR+rwQjKD258V0CJ0TfhiNdFv1lNtunydkNkJOg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1B2jlTzmkdge69WxB/YBZXqiM9kZOcT+fw5A5NNfm4g=; b=9wjzpajksEV08L3wFHPVhcdqtsmSw5DyFJ65LG4dPdIi3Qn05aLuCWaI51hBmueTSCTaVpCDUNdGQ7IEckeAPA+BeorgbBmZiVs0gJT1T+/c0XS5nqrouOznk5E94RQibYQQ8Ch/iV06uSvhqUE8f8YBUH91rUm+79udtoOaOEM= Received: from AS9PR05CA0295.eurprd05.prod.outlook.com (2603:10a6:20b:492::29) by GV1PR08MB7316.eurprd08.prod.outlook.com (2603:10a6:150:1f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.35; Fri, 6 Oct 2023 11:56:13 +0000 Received: from AM7EUR03FT057.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:492:cafe::a5) by AS9PR05CA0295.outlook.office365.com (2603:10a6:20b:492::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.33 via Frontend Transport; Fri, 6 Oct 2023 11:56:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT057.mail.protection.outlook.com (100.127.140.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6863.31 via Frontend Transport; Fri, 6 Oct 2023 11:56:13 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 6 Oct 2023 11:56:12 +0000 Received: from e127754.arm.com (10.57.2.208) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 6 Oct 2023 11:56:12 +0000 From: To: CC: , Subject: [PATCH 2/3] [GCC] arm: vst1_types_x3 ACLE intrinsics Date: Fri, 6 Oct 2023 12:55:59 +0100 Message-ID: <20231006115600.20630-3-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231006115600.20630-1-Ezra.Sitorus@arm.com> References: <20231006115600.20630-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT057:EE_|GV1PR08MB7316:EE_|DBAEUR03FT056:EE_|DB9PR08MB6538:EE_ X-MS-Office365-Filtering-Correlation-Id: bf59192f-25d5-4849-05a0-08dbc6634354 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: fYFeXU+EtN09mlBzZlvRxPtP1i/0ECWVgETtvQVPI1vQMKMJ9NBdUDtfIZ/HpvctNN6Wwid/phjAw5KLDT9IamJ41fpzMqo5W+4YsFjTpSRd5LABtXJsO3wMU1MW8fMkiYZz2D/K/eO3AEVFwbOWeBQszCrFuxJNiUzDTH4ohpcC6OSP6SkCHXb96/wCt97e3o9rABFytyXeQm9/CBBD+RbBrLujoSGTefAuXfwkArmWzfcI0KdkNv8D4jr7zAQd7Fh4igahTQWifnIXyRpqS6GWDG0cdV9vLNkjchKM47bfUUstWHJo2WjB37bVHiA58JhRLoTV73KOcsYcYVVIEXkXOpy9N5kmDSU6eFRtIZpAD05Mnhak5lbXfsjV9HaQ24LUvhwbVKiWzk7KMpf80G+QHriBR1YXFKKDAWCyPnBHQIr0LM3mvJjRDJjPPkbvZBUvMcqOYY8QzkP++Fu9hVfvtigWiAcj8Mo1FXNZi+sg++4JWXJr1zBI3XmTeTUkWXeBva8p08s6PH6KDQ5Vf9zTIWpBhghJOTyCsC6nnn0P9uLK+Wn9unOvGoo1xqjs3J48nHe4CSCaPrLURdtqME/y8D225EMLwbv2FYICuUMryxLoOEaaReHahqngq+g7JtYFdWoprEnb9QFsIPsH4tNcVYNyhAGu4hb278nDjmmdpxaJkqGqGeesQEeBHtgxCNyKxe8iWXXDgNHCwTQWqT6anueq5Mpzso89wZCeJro+DdoU76S8+SW+jcIhuforjYnkJ3m0Ox13L8OILPDJPJ/huuzSRw2InjZcFqoAlxI= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(346002)(136003)(396003)(376002)(39860400002)(230922051799003)(1800799009)(82310400011)(451199024)(64100799003)(186009)(40470700004)(36840700001)(46966006)(84970400001)(5660300002)(8676002)(30864003)(2876002)(2906002)(4326008)(8936002)(41300700001)(70206006)(70586007)(2616005)(316002)(6916009)(40460700003)(54906003)(36860700001)(40480700001)(336012)(426003)(6666004)(36756003)(26005)(7696005)(1076003)(86362001)(83380400001)(356005)(82740400003)(81166007)(47076005)(478600001)(966005)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB7316 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT056.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: cd41f2b6-e669-4380-2bd9-08dbc6633d2f X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HJsHGXKW339I+k5I6/XeSad7i34Lqnkffg6aN1ftgSVrxOwNaFO8p4ibCkpJnBrN48QO3DfpASKDFWA/tgD9VtOgM6Z/DSnSV6P8wDnn2D2qIuvm0MC8KBlsxy8uOJGMLAZYpiwZUtrtCGqzM//rdBmRmYAS9Rjb9hgL1YzRhJbJGZEYT/0Zu1pqkMWarLjLrf5QpOsuw+616UtN9C8RNc7+LB2K2ET0lPmSL8rCLrHkfxJo2agBQ+f1xecL7BsZ57u9SHefrtBfEkCYi+sEBzfr30r6tg5RL1Uq05pz/Xmv5ujbGkvnw9yMJd3uMBUI1uMlQP7DE33/mQ+cnP7AsboG4Dye0hUtEoEgQBI2qUcs12wBIVBzjU3qtCKNPsqGS6kYqJpzOOzWmA7kW/d30JXtaZJldY169eeAOD3T4aSoYjiXUbwBgKXYvxuUYJC43uYmC8+J2nM4hkumNOlppFFAQP6xikhW7GmbZKZB/lqW8F4cLWTnH3DhB/AM5713eUfFzXkv/38UxVvp5iGT2Ta5HeCpy7JfRVzQMEG6S9ZG7hpO2uCoNcbRTTfMM3Ykn+Eftjw5BM2C4ewdqr+9U2zYgj4Gr2jyOmFGoqYR9gm62Niu70fN8edyD7t1RQ2TOR2pVWyRJ1IZDzQYLGRh5dbhWRJL9Qh8DunjPpLJNT0Byxs27tac+PNVNAfygrpjysR1SdXNHk3IZPh/gxY+aj3D/0HyQk/LegANvSvyfbJ6F9X7q1g6ae6hi2z3qXWZ3GmM58nnkIYQ4svTv8V7xw== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(346002)(39860400002)(376002)(396003)(136003)(230922051799003)(451199024)(1800799009)(82310400011)(64100799003)(186009)(40470700004)(46966006)(36840700001)(84970400001)(2876002)(30864003)(40460700003)(2906002)(8676002)(8936002)(4326008)(41300700001)(5660300002)(40480700001)(36756003)(54906003)(70206006)(478600001)(86362001)(7696005)(6666004)(1076003)(2616005)(966005)(316002)(70586007)(82740400003)(81166007)(36860700001)(336012)(426003)(26005)(6916009)(83380400001)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2023 11:56:23.6699 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf59192f-25d5-4849-05a0-08dbc6634354 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT056.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6538 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779007225778922316 X-GMAIL-MSGID: 1779007225778922316 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1 intrinsic for arm32. This patch adds the _x3 variants of the vst1 intrinsic. ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/ ISA documents are at https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New. (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New. (vst1_f16_x3, vst1_f32_x3): New. (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New. (vst1_bf16_x3): New. * config/arm/arm_neon_builtins.def (vst1_x3): New entries. * config/arm/neon.md (vst1_x3): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1_base_xN_1.c: Add new test. * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new test. * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new test. * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new test. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/neon.md | 10 ++ .../gcc.target/arm/simd/vst1_base_xN_1.c | 63 +++++++++- .../gcc.target/arm/simd/vst1_bf16_xN_1.c | 7 +- .../gcc.target/arm/simd/vst1_fp16_xN_1.c | 7 +- .../gcc.target/arm/simd/vst1_p64_xN_1.c | 7 +- 7 files changed, 202 insertions(+), 7 deletions(-) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 4bd6093281b..b01171e5966 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11250,6 +11250,14 @@ vst1_p64_x2 (poly64_t * __a, poly64x1x2_t __b) __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_p64_x3 (poly64_t * __a, poly64x1x3_t __b) +{ + union { poly64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11311,6 +11319,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b) __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_s16_x3 (int16_t * __a, int16x4x3_t __b) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_s32_x3 (int32_t * __a, int32x2x3_t __b) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_s64_x3 (int64_t * __a, int64x1x3_t __b) +{ + union { int64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o); +} + #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11345,6 +11385,24 @@ vst1_f32_x2 (float32_t * __a, float32x2x2_t __b) __builtin_neon_vst1_x2v2sf ((__builtin_neon_sf *) __a, __bu.__o); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_f16_x3 (float16_t * __a, float16x4x3_t __b) +{ + union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v4hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_f32_x3 (float32_t * __a, float32x2x3_t __b) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v2sf ((__builtin_neon_sf *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_u8 (uint8_t * __a, uint8x8_t __b) @@ -11405,6 +11463,38 @@ vst1_u64_x2 (uint64_t * __a, uint64x1x2_t __b) __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_u8_x3 (uint8_t * __a, uint8x8x3_t __b) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_u16_x3 (uint16_t * __a, uint16x4x3_t __b) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_u32_x3 (uint32_t * __a, uint32x2x3_t __b) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v2si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_u64_x3 (uint64_t * __a, uint64x1x3_t __b) +{ + union { uint64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_p8 (poly8_t * __a, poly8x8_t __b) @@ -11435,6 +11525,22 @@ vst1_p16_x2 (poly16_t * __a, poly16x4x2_t __b) __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_p8_x3 (poly8_t * __a, poly8x8x3_t __b) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_p16_x3 (poly16_t * __a, poly16x4x3_t __b) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o); +} + #pragma GCC push_options #pragma GCC target ("fpu=crypto-neon-fp-armv8") __extension__ extern __inline void @@ -20184,6 +20290,14 @@ vst1_bf16_x2 (bfloat16_t * __a, bfloat16x4x2_t __b) __builtin_neon_vst1_x2v4hf ((__builtin_neon_bf *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1_bf16_x3 (bfloat16_t * __a, bfloat16x4x3_t __b) +{ + union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b }; + __builtin_neon_vst1_x3v4hf ((__builtin_neon_bf *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 7aef6f958cd..e33b3429f65 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -309,6 +309,7 @@ VAR12 (LOAD1LANE, vld1_lane, VAR10 (LOAD1, vld1_dup, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR14 (STORE1, vst1, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 7a10e2cb61e..3d1d2aa7d06 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5135,6 +5135,16 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_store1_2reg")] ) +(define_insn "neon_vst1_x3" + [(set (match_operand:EI 0 "neon_struct_operand" "=Um") + (unspec:EI [(match_operand:EI 1 "s_register_operand" "w") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST1))] + "TARGET_NEON" + "vst1.\t%h1, %A0" + [(set_attr "type" "neon_store1_3reg")] +) + (define_insn "neon_vst1" [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um") (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")] diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c index 575897fa422..5f820a6a496 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c @@ -60,8 +60,63 @@ void test_vst1_p16_x2 (poly16_t * ptr, poly16x4x2_t val) vst1_p16_x2 (ptr, val); } +void test_vst1_u8_x3 (uint8_t * ptr, uint8x8x3_t val) +{ + vst1_u8_x3 (ptr, val); +} + +void test_vst1_u16_x3 (uint16_t * ptr, uint16x4x3_t val) +{ + vst1_u16_x3 (ptr, val); +} + +void test_vst1_u32_x3 (uint32_t * ptr, uint32x2x3_t val) +{ + vst1_u32_x3 (ptr, val); +} + +void test_vst1_u64_x3 (uint64_t * ptr, uint64x1x3_t val) +{ + vst1_u64_x3 (ptr, val); +} + +void test_vst1_s8_x3 (int8_t * ptr, int8x8x3_t val) +{ + vst1_s8_x3 (ptr, val); +} + +void test_vst1_s16_x3 (int16_t * ptr, int16x4x3_t val) +{ + vst1_s16_x3 (ptr, val); +} + +void test_vst1_s32_x3 (int32_t * ptr, int32x2x3_t val) +{ + vst1_s32_x3 (ptr, val); +} + +void test_vst1_s64_x3 (int64_t * ptr, int64x1x3_t val) +{ + vst1_s64_x3 (ptr, val); +} + +void test_vst1_f32_x3 (float32_t * ptr, float32x2x3_t val) +{ + vst1_f32_x3 (ptr, val); +} + +void test_vst1_p8_x3 (poly8_t * ptr, poly8x8x3_t val) +{ + vst1_p8_x3 (ptr, val); +} + +void test_vst1_p16_x3 (poly16_t * ptr, poly16x4x3_t val) +{ + vst1_p16_x3 (ptr, val); +} + -/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c index 213fd20ee65..a3a00ead468 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c @@ -10,4 +10,9 @@ void test_vst1_bf16_x2 (bfloat16_t * ptr, bfloat16x4x2_t val) vst1_bf16_x2 (ptr, val); } -/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +void test_vst1_bf16_x3 (bfloat16_t * ptr, bfloat16x4x3_t val) +{ + vst1_bf16_x3 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c index 523aec92db2..0a6863e24c6 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c @@ -10,4 +10,9 @@ void test_vst1_f16_x2 (float16_t * ptr, float16x4x2_t val) vst1_f16_x2 (ptr, val); } -/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +void test_vst1_f16_x3 (float16_t * ptr, float16x4x3_t val) +{ + vst1_f16_x3 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c index f590ebd7b94..5dbd6049bc9 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c @@ -10,4 +10,9 @@ void test_vst1_p64_x2 (poly64_t * ptr, poly64x1x2_t val) vst1_p64_x2 (ptr, val); } -/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ \ No newline at end of file +void test_vst1_p64_x3 (poly64_t * ptr, poly64x1x3_t val) +{ + vst1_p64_x3 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ \ No newline at end of file