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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h11-20020a170906590b00b00992bfd00fdbsi6575018ejq.971.2023.09.23.20.46.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Sep 2023 20:46:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="E+BJ3hJ/"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D2FE3858284 for ; Sun, 24 Sep 2023 03:45:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 5047E3858CDB for ; Sun, 24 Sep 2023 03:45:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5047E3858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695527134; x=1727063134; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=bldLzylFAD25lzuzmPEpCWRJWsZbcfUeZwm4cWD1GYY=; b=E+BJ3hJ/my7vUFwiU+bjWyPsPHEpKRdFsWo+ZOvya1JlfohR+lCKZny9 wwhbS0fJoFVQHu0XDTntUNE2meHnx4VdAf6fX3i/mLhPSawXVIf+SwWz8 Zv4Is5prxLWsPFcC04aLAz2d49mlmDZE1kDfi+oXdZnmDLVG5MI6vdygQ spY0kcHKpDb5z1/sJDl8ygWu5+7MY3hHH1ncRTdmmaHxpfYZWuxLeu/gz gMJtBqfOdxOFKKD23CyGZz7U4sbrJgrP+R35KdpKXgnhtcOBeKZoUu6m7 GLZp+iNOtGiW0nXkLsELu14kZ3I+ELdb/PlecXb3FcXyjUSNmKJkllZXc g==; X-IronPort-AV: E=McAfee;i="6600,9927,10842"; a="467357766" X-IronPort-AV: E=Sophos;i="6.03,171,1694761200"; d="scan'208";a="467357766" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2023 20:45:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10842"; a="741538696" X-IronPort-AV: E=Sophos;i="6.03,171,1694761200"; d="scan'208";a="741538696" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 23 Sep 2023 20:45:30 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id AF6511005129; Sun, 24 Sep 2023 11:45:29 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com, patrick@rivosinc.com Subject: [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init Date: Sun, 24 Sep 2023 11:45:28 +0800 Message-Id: <20230924034528.1827780-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777889092436375511 X-GMAIL-MSGID: 1777889092436375511 From: Pan Li When broadcast the reperated element, we take the mask machine mode by mistake. This patch would like to fix it by leveraging the machine mode of the element. The below test case in RV32 will be fixed. * gcc/testsuite/gfortran.dg/overload_5.f90 PR target/111546 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vector_init_merge_repeating_sequence): Bugfix Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index c2466b1354f..6fcbd1622af 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2059,7 +2059,7 @@ expand_vector_init_merge_repeating_sequence (rtx target, uint64_t full_nelts = builder.full_nelts ().to_constant (); /* Step 1: Broadcast the first pattern. */ - rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))}; + rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))}; emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()), UNARY_OP, ops); /* Step 2: Merge the rest iteration of pattern. */