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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id kb10-20020a1709070f8a00b0099ced4e20b2si3397431ejc.457.2023.09.22.03.58.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 03:58:47 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="hLH0Z/+C"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C1F9385CCBF for ; Fri, 22 Sep 2023 10:57:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 5F5A83858281 for ; Fri, 22 Sep 2023 10:56:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5F5A83858281 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695380202; x=1726916202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OaAPJbqPqCoT5U8cWrAAKHXsej5m+V+tThp5anh1l6A=; b=hLH0Z/+CSn4wo1byZiRe1TDSmjf8xLbXm2xSWo5cLkyAaRDmRHrX7hua axoS1Q4ojasdzQ42bohzZdvgT64M7tsTQHKwGtGH/SKgy5bA1rmEFL51n LTf9ge7+uSsH+ZcLbHHkMrOm0mt/i8lE5ufUjrYh5oPUYPZAsNLnPQGpy p/KCI5A4eu9uSRtoYp5qRR+6QlODoqQf2DJYy5HCzGLcsy6e0QoE332pa SUSti/eIA5y/KXqa+g7Tyn+zYmP2rf69LPHczdIfOXzy3Q39g0lRFplgk 1dtjTQTh5YJ8+BheH294yVqonK66GsFXrlKb143mHqW5/jzkNzYukB54o w==; X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="379680797" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="379680797" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 03:56:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="782615904" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="782615904" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2023 03:56:35 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id AD2B3100513A; Fri, 22 Sep 2023 18:56:31 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, vmakarov@redhat.com, jakub@redhat.com, Kong Lingling , Hongtao Liu Subject: [PATCH 05/13] [APX EGPR] Add register and memory constraints that disallow EGPR Date: Fri, 22 Sep 2023 18:56:23 +0800 Message-Id: <20230922105631.2298849-6-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230922105631.2298849-1-hongyu.wang@intel.com> References: <20230922105631.2298849-1-hongyu.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777735121830623690 X-GMAIL-MSGID: 1777735121830623690 From: Kong Lingling For APX, as we extended the GENERAL_REG_CLASS, new constraints are needed to restrict insns that cannot adopt EGPR either in its reg or memory operands. We added a series of constraints for general/backend ones that related to GPR usage. All of them are prefixed with "j" to indicate the constraints does not allow EGPR. gcc/ChangeLog: * config/i386/constraints.md (jr): New register constraint that prohibits EGPR. (jR): Constraint that force usage of EGPR. (jm): New memory constraint that prohibits EGPR. (ja): Likewise for Bm constraint. (jb): Likewise for Tv constraint. (j<): New auto-dec memory constraint that prohibits EGPR. (j>): Likewise for ">" constraint. (jo): Likewise for "o" constraint. (jv): Likewise for "V" constraint. (jp): Likewise for "p" constraint. * config/i386/i386.h (enum reg_class): Add new reg class GENERAL_GPR16. Co-authored-by: Hongyu Wang Co-authored-by: Hongtao Liu --- gcc/config/i386/constraints.md | 59 +++++++++++++++++++++++++++++++++- gcc/config/i386/i386.h | 4 +++ 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index fd490f39110..36c268d7f9b 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -19,7 +19,7 @@ ;;; Unused letters: ;;; H -;;; h j z +;;; j z ;; Integer register constraints. ;; It is not necessary to define 'r' here. @@ -371,3 +371,60 @@ (define_address_constraint "Tv" (define_address_constraint "Ts" "Address operand without segment register" (match_operand 0 "address_no_seg_operand")) + +;; Constraint that force to use EGPR, can only adopt to register class. +(define_register_constraint "jR" "GENERAL_REGS") + +(define_register_constraint "jr" + "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS") + +(define_memory_constraint "jm" + "@internal memory operand without GPR32." + (and (match_operand 0 "memory_operand") + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_constraint "j<" + "@internal auto-dec memory operand without GPR32." + (and (and (match_code "mem") + (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC") + (match_test "GET_CODE (XEXP (op, 0)) == POST_DEC"))) + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_constraint "j>" + "@internal auto-dec memory operand without GPR32." + (and (and (match_code "mem") + (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_INC") + (match_test "GET_CODE (XEXP (op, 0)) == POST_INC"))) + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_memory_constraint "jo" + "@internal offsetable memory operand without GPR32." + (and (and (match_code "mem") + (match_test "offsettable_nonstrict_memref_p (op)")) + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_constraint "jV" + "@internal non-offsetable memory operand without GPR32." + (and (and (match_code "mem") + (match_test "memory_address_addr_space_p (GET_MODE (op), + XEXP (op, 0), + MEM_ADDR_SPACE (op))") + (not (match_test "offsettable_nonstrict_memref_p (op)"))) + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_address_constraint "jp" + "@internal general address operand without GPR32" + (and (match_test "address_operand (op, VOIDmode)") + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_special_memory_constraint "ja" + "@internal vector memory operand without GPR32." + (and (match_operand 0 "vector_memory_operand") + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 215f6b8db55..66b8764e82b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1295,6 +1295,8 @@ enum reg_class %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */ + GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp + %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ FLOAT_REGS, SSE_FIRST_REG, @@ -1357,6 +1359,7 @@ enum reg_class "INDEX_REGS", \ "LEGACY_REGS", \ "GENERAL_REGS", \ + "GENERAL_GPR16", \ "FP_TOP_REG", "FP_SECOND_REG", \ "FLOAT_REGS", \ "SSE_FIRST_REG", \ @@ -1395,6 +1398,7 @@ enum reg_class { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \ { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */ \ + { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \ { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \