From patchwork Fri Sep 22 10:56:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 143347 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a55:b0:13f:353d:d1ed with SMTP id 21csp4565566rwb; Fri, 22 Sep 2023 03:57:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE+LqvoWbTVz4r/ePFPjUM97h6L0b9w+hj+e+7B/CLcY6szG3xVhaKf514wPdAiD+G58IzZ X-Received: by 2002:aa7:d487:0:b0:522:b112:6254 with SMTP id b7-20020aa7d487000000b00522b1126254mr7320560edr.4.1695380265437; Fri, 22 Sep 2023 03:57:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695380265; cv=none; d=google.com; s=arc-20160816; b=IMvQ6pH5HHcF0K+Y9h/e5OwqQd+u/Eu7kxk2S8xDHYSG80MUr6HWgDjpd5boAx+6il kM1dmolvNtYbInOqg1u2JJAPYSoRovjfdtM5J+YoY/1/KRdhb8EkYfhV/4Ry2Wka0xxG yQ2TlP0WmljivxMV3jEXrBIWDZO2FATBq0NS5VhhxB0aEjSV3hSe1DXe7wF492Bw5oB9 2FVCFWS5dw68bl1W908rKtq6OBX3GZckkmDYTKOAQGBQzgJRwb1c5sdp1Z+l8IKYmPws 05JFqj+86dcl8ZzyvDIZhKt2rcdlvtPMFMZyrbqEnpOr/dt+lSfRVTceQVNyH97AhlRy NB0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=dEWfpUIue0vJ/aESz85wp7iWZ6vUgByNuGRFx3x5EtY=; fh=ohmInM8pkhFahNid/tIrxUIOBXWhoriwAcUbKKgAH4Q=; b=K6BMl+xvILD8j7jHGGVDrvgSDEUSnQZrcHRbAGS7csQNxMeu33ZO7HqehzUX4WEEJD LmQ5KhUHpaNQp5M89Y/FwwU4msgdwH5UY5Zqik/RY5x4eEpB5h95K2kvix3vo392BOwE 21aeMChTBXq62ZVr8V9hw4gvajfGASjFs7aS1dLMu1S0xoSb9zHJt2gkE13fcudZlZph oHvn1NjrgPZU1289SiIYEyBFNICcKxEvk/CXaDY99tY55w6sCd5AcMBrSQwO/A/cZ/+P kTRBCXZ/6SiDXpyyPsuhP4t/0xclw0XAssHq5NWSBrELP7ufVVU9FHiRACIKxqGi18LZ bMTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=C5EEaRYZ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id e9-20020aa7d7c9000000b0053303a2deabsi3124243eds.200.2023.09.22.03.57.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 03:57:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=C5EEaRYZ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 989C6386183C for ; Fri, 22 Sep 2023 10:57:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 029123858D33 for ; Fri, 22 Sep 2023 10:56:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 029123858D33 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695380198; x=1726916198; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+hdqcnhfWSR7sZ5k9232S16W96z+kJFSzyIu53WpNfo=; b=C5EEaRYZcNBIDenGyrXHHyg7VSa1Un0depokruiNWhHpW9seIPedW5eB xmOsGct1z95Knn1zWlQCRzPu0oxAZVaGLoTGQARobKHLOcme/D/lw2x9i Kx6W/IhPOk4wYmc5HvdrYit/q6dqBxnnnh5uq63+tnNpBnlEpOe/d+prT i9GvL8bDGsD134gvq/ePldEWtrKIvyKHeL6opze5vk7eNlLNfwob+s708 ia7ra0NlI0BsSpTHehd7CH4MTlaYhMwcY45mL+ZPgKs+wHC5N8A2Kj8cK KRIEiOnyGibMQPW8uOsiYn6i7Q3kZ4A71cmWUO4y9QO3M+mjlsA/CydEE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="379680783" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="379680783" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 03:56:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="782615872" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="782615872" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2023 03:56:32 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id A39291005137; Fri, 22 Sep 2023 18:56:31 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, vmakarov@redhat.com, jakub@redhat.com, Kong Lingling , Hongtao Liu Subject: [PATCH 02/13] [APX EGPR] middle-end: Add index_reg_class with insn argument. Date: Fri, 22 Sep 2023 18:56:20 +0800 Message-Id: <20230922105631.2298849-3-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230922105631.2298849-1-hongyu.wang@intel.com> References: <20230922105631.2298849-1-hongyu.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777735057026456886 X-GMAIL-MSGID: 1777735057026456886 Like base_reg_class, INDEX_REG_CLASS also does not support backend insn. Add index_reg_class with insn argument for lra/reload usage. gcc/ChangeLog: * addresses.h (index_reg_class): New wrapper function like base_reg_class. * doc/tm.texi: Document INSN_INDEX_REG_CLASS. * doc/tm.texi.in: Ditto. * lra-constraints.cc (index_part_to_reg): Pass index_class. (process_address_1): Calls index_reg_class with curr_insn and replace INDEX_REG_CLASS with its return value index_cl. * reload.cc (find_reloads_address): Likewise. (find_reloads_address_1): Likewise. Co-authored-by: Kong Lingling Co-authored-by: Hongtao Liu --- gcc/addresses.h | 10 ++++++++++ gcc/doc/tm.texi | 7 +++++++ gcc/doc/tm.texi.in | 7 +++++++ gcc/lra-constraints.cc | 17 +++++++++-------- gcc/reload.cc | 4 ++-- 5 files changed, 35 insertions(+), 10 deletions(-) diff --git a/gcc/addresses.h b/gcc/addresses.h index 2c92927bd51..08bf39cd56c 100644 --- a/gcc/addresses.h +++ b/gcc/addresses.h @@ -51,6 +51,16 @@ base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, #endif } +inline enum reg_class +index_reg_class (rtx_insn *insn ATTRIBUTE_UNUSED = NULL) +{ +#ifdef INSN_INDEX_REG_CLASS + return INSN_INDEX_REG_CLASS (insn); +#else + return INDEX_REG_CLASS; +#endif +} + /* Wrapper function to unify target macros REGNO_MODE_CODE_OK_FOR_BASE_P, REGNO_MODE_OK_FOR_REG_BASE_P, REGNO_MODE_OK_FOR_BASE_P and REGNO_OK_FOR_BASE_P. diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 5b1e2a11f89..c566f7a1105 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -2582,6 +2582,13 @@ address where its value is either multiplied by a scale factor or added to another register (as well as added to a displacement). @end defmac +@defmac INSN_INDEX_REG_CLASS (@var{insn}) +A C expression whose value is the register class to which a valid +index register for a specified @var{insn} must belong. This macro is +used when some backend insns may have limited usage of index register +compared with other insns. +@end defmac + @defmac REGNO_OK_FOR_BASE_P (@var{num}) A C expression which is nonzero if register number @var{num} is suitable for use as a base register in operand addresses. diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index f6e63ad8871..3182d0d7c75 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -2164,6 +2164,13 @@ address where its value is either multiplied by a scale factor or added to another register (as well as added to a displacement). @end defmac +@defmac INSN_INDEX_REG_CLASS (@var{insn}) +A C expression whose value is the register class to which a valid +index register for a specified @var{insn} must belong. This macro is +used when some backend insns may have limited usage of index register +compared with other insns. +@end defmac + @defmac REGNO_OK_FOR_BASE_P (@var{num}) A C expression which is nonzero if register number @var{num} is suitable for use as a base register in operand addresses. diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 6dc77af86cd..0c8e28e0194 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -3399,12 +3399,12 @@ base_plus_disp_to_reg (struct address_info *ad, rtx disp) /* Make reload of index part of address AD. Return the new pseudo. */ static rtx -index_part_to_reg (struct address_info *ad) +index_part_to_reg (struct address_info *ad, enum reg_class index_class) { rtx new_reg; new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, - INDEX_REG_CLASS, NULL, "index term"); + index_class, NULL, "index term"); expand_mult (GET_MODE (*ad->index), *ad->index_term, GEN_INT (get_index_scale (ad)), new_reg, 1); return new_reg; @@ -3659,13 +3659,14 @@ process_address_1 (int nop, bool check_only_p, /* If INDEX_REG_CLASS is assigned to base_term already and isn't to index_term, swap them so to avoid assigning INDEX_REG_CLASS to both when INDEX_REG_CLASS is a single register class. */ + enum reg_class index_cl = index_reg_class (curr_insn); if (ad.base_term != NULL && ad.index_term != NULL - && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 + && ira_class_hard_regs_num[index_cl] == 1 && REG_P (*ad.base_term) && REG_P (*ad.index_term) - && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) - && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) + && in_class_p (*ad.base_term, index_cl, NULL) + && ! in_class_p (*ad.index_term, index_cl, NULL)) { std::swap (ad.base, ad.index); std::swap (ad.base_term, ad.index_term); @@ -3689,7 +3690,7 @@ process_address_1 (int nop, bool check_only_p, } if (ad.index_term != NULL && process_addr_reg (ad.index_term, check_only_p, - before, NULL, INDEX_REG_CLASS)) + before, NULL, index_cl)) change_p = true; /* Target hooks sometimes don't treat extra-constraint addresses as @@ -3798,7 +3799,7 @@ process_address_1 (int nop, bool check_only_p, GET_CODE (*ad.index), curr_insn); - lra_assert (INDEX_REG_CLASS != NO_REGS); + lra_assert (index_cl != NO_REGS); new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "disp"); lra_emit_move (new_reg, *ad.disp); *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), @@ -3894,7 +3895,7 @@ process_address_1 (int nop, bool check_only_p, changed pseudo on the equivalent memory and a subreg of the pseudo onto the memory of different mode for which the scale is prohibitted. */ - new_reg = index_part_to_reg (&ad); + new_reg = index_part_to_reg (&ad, index_cl); *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), *ad.base_term, new_reg); } diff --git a/gcc/reload.cc b/gcc/reload.cc index 72f7e27af15..66b484b12fa 100644 --- a/gcc/reload.cc +++ b/gcc/reload.cc @@ -5114,7 +5114,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad, /* Reload the displacement into an index reg. We assume the frame pointer or arg pointer is a base reg. */ find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), - INDEX_REG_CLASS, GET_MODE (ad), opnum, + index_reg_class (insn), GET_MODE (ad), opnum, type, ind_levels); return 0; } @@ -5514,7 +5514,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as, bool reloaded_inner_of_autoinc = false; if (context == 1) - context_reg_class = INDEX_REG_CLASS; + context_reg_class = index_reg_class (insn); else context_reg_class = base_reg_class (mode, as, outer_code, index_code, insn);