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[8.43.85.97]) by mx.google.com with ESMTPS id sa41-20020a1709076d2900b009ae75480721si927320ejc.906.2023.09.22.00.53.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 00:53:17 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 92C50385735A for ; Fri, 22 Sep 2023 07:52:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id A1FB63858D37 for ; Fri, 22 Sep 2023 07:52:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A1FB63858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp65t1695369115t5snpn50 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 22 Sep 2023 15:51:54 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBfmtZLkRVo5uBbjHTVinQrkoza2zGMo3Qtslz9wdw/ZkvTwLMZVHM gOo3LYF8sQpLTJg61M+FTNztFm6HHcmSQbmh1dCCLlP6cBRRx4AImaKtXUdAiHW1vXj8rZk jHAU4Rxs1V5hn6fHjjTQxsTHddFrRsTRt2G1v2NeCMkIUFQkdRdFa2jrRgDxDu1hvE5mMV1 qgolMtR/lRlSuGUCSISoJG+zCkf5DNja4gV6xgCf3C5MutM5NrXevBUeMwC5vgfL69R1Zjx 5rpnsBUDLcL33+mJsHRIfMqXbkbYWhcNf8D1n+dfYXQZeaEAXGI1FYTYcG9s3UKga6kCmPm 3KSO4mJ2S6UcmmS0Kff3nkJmScX+s3PeXZc/s/aVB7z0MY7MvfN8F28EqTL2xB4ehG7jhLt P833CLvlfGLRsUVYyoR66A== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15831639748645397876 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add VLS conditional patterns support Date: Fri, 22 Sep 2023 15:51:53 +0800 Message-Id: <20230922075153.2220810-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777723452109486364 X-GMAIL-MSGID: 1777723452109486364 Regression passed. Committed. gcc/ChangeLog: * config/riscv/autovec.md: Add VLS conditional patterns. * config/riscv/riscv-protos.h (expand_cond_unop): Ditto. (expand_cond_binop): Ditto. (expand_cond_ternop): Ditto. * config/riscv/riscv-v.cc (expand_cond_unop): Ditto. (expand_cond_binop): Ditto. (expand_cond_ternop): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS conditional tests. * gcc.target/riscv/rvv/autovec/vls/cond_add-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_add-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_and-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_div-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_div-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_max-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_max-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_min-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_min-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_not-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c: New test. --- gcc/config/riscv/autovec.md | 200 +++++++----------- gcc/config/riscv/riscv-protos.h | 3 + gcc/config/riscv/riscv-v.cc | 45 ++++ .../riscv/rvv/autovec/vls/cond_add-1.c | 104 +++++++++ .../riscv/rvv/autovec/vls/cond_add-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_and-1.c | 104 +++++++++ .../riscv/rvv/autovec/vls/cond_div-1.c | 58 +++++ .../riscv/rvv/autovec/vls/cond_div-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_fma-1.c | 62 ++++++ .../riscv/rvv/autovec/vls/cond_fma-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_fms-1.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_fnma-1.c | 62 ++++++ .../riscv/rvv/autovec/vls/cond_fnma-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_fnms-1.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_ior-1.c | 104 +++++++++ .../riscv/rvv/autovec/vls/cond_max-1.c | 104 +++++++++ .../riscv/rvv/autovec/vls/cond_max-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_min-1.c | 104 +++++++++ .../riscv/rvv/autovec/vls/cond_min-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_mod-1.c | 58 +++++ .../riscv/rvv/autovec/vls/cond_mul-1.c | 104 +++++++++ .../riscv/rvv/autovec/vls/cond_mul-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_neg-1.c | 62 ++++++ .../riscv/rvv/autovec/vls/cond_neg-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_not-1.c | 62 ++++++ .../riscv/rvv/autovec/vls/cond_shift-1.c | 57 +++++ .../riscv/rvv/autovec/vls/cond_shift-2.c | 56 +++++ .../riscv/rvv/autovec/vls/cond_sub-1.c | 104 +++++++++ .../riscv/rvv/autovec/vls/cond_sub-2.c | 50 +++++ .../riscv/rvv/autovec/vls/cond_xor-1.c | 104 +++++++++ .../gcc.target/riscv/rvv/autovec/vls/def.h | 70 ++++++ 31 files changed, 2059 insertions(+), 118 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index b92cb7a5d0f..6f35fb1bd9e 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1492,18 +1492,15 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (any_int_unop:VI - (match_operand:VI 2 "register_operand")) - (match_operand:VI 3 "autovec_else_operand")] + (any_int_unop:V_VLSI + (match_operand:V_VLSI 2 "register_operand")) + (match_operand:V_VLSI 3 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], - operands[3], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_unop (icode, operands); DONE; }) @@ -1530,18 +1527,15 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (any_float_unop_nofrm:VF - (match_operand:VF 2 "register_operand")) - (match_operand:VF 3 "autovec_else_operand")] + (any_float_unop_nofrm:V_VLSF + (match_operand:V_VLSF 2 "register_operand")) + (match_operand:V_VLSF 3 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], - operands[3], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_unop (icode, operands); DONE; }) @@ -1568,19 +1562,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (any_shift:VI - (match_operand:VI 2 "register_operand") - (match_operand:VI 3 "vector_shift_operand")) - (match_operand:VI 4 "autovec_else_operand")] + (any_shift:V_VLSI + (match_operand:V_VLSI 2 "register_operand") + (match_operand:V_VLSI 3 "vector_shift_operand")) + (match_operand:V_VLSI 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1609,19 +1600,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (any_int_binop_no_shift:VI - (match_operand:VI 2 "") - (match_operand:VI 3 "")) - (match_operand:VI 4 "autovec_else_operand")] + (any_int_binop_no_shift:V_VLSI + (match_operand:V_VLSI 2 "") + (match_operand:V_VLSI 3 "")) + (match_operand:V_VLSI 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1650,19 +1638,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (any_float_binop:VF - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "autovec_else_operand")] + (any_float_binop:V_VLSF + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand")) + (match_operand:V_VLSF 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1689,19 +1674,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (any_float_binop_nofrm:VF - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "autovec_else_operand")] + (any_float_binop_nofrm:V_VLSF + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand")) + (match_operand:V_VLSF 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_ (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1729,19 +1711,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_fma" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (match_operand:VI 2 "register_operand") - (match_operand:VI 3 "register_operand") - (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "autovec_else_operand")] + (match_operand:V_VLSI 2 "register_operand") + (match_operand:V_VLSI 3 "register_operand") + (match_operand:V_VLSI 4 "register_operand") + (match_operand:V_VLSI 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fma (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul_plus (mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1762,19 +1741,16 @@ }) (define_expand "cond_fnma" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (match_operand:VI 2 "register_operand") - (match_operand:VI 3 "register_operand") - (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "autovec_else_operand")] + (match_operand:V_VLSI 2 "register_operand") + (match_operand:V_VLSI 3 "register_operand") + (match_operand:V_VLSI 4 "register_operand") + (match_operand:V_VLSI 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fnma (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_minus_mul (mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1802,19 +1778,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_fma" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fma (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul (PLUS, mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1835,19 +1808,16 @@ }) (define_expand "cond_fnma" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fnma (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul_neg (PLUS, mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1868,19 +1838,16 @@ }) (define_expand "cond_fms" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fms (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul (MINUS, mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1901,19 +1868,16 @@ }) (define_expand "cond_fnms" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand: 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fnms (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul_neg (MINUS, mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 3eec72b6703..34becfbaba8 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -485,6 +485,9 @@ void expand_cond_len_ternop (unsigned, rtx *); void prepare_ternary_operands (rtx *); void expand_lanes_load_store (rtx *, bool); void expand_fold_extract_last (rtx *); +void expand_cond_unop (unsigned, rtx *); +void expand_cond_binop (unsigned, rtx *); +void expand_cond_ternop (unsigned, rtx *); /* Rounding mode bitfield for fixed point VXRM. */ enum fixed_point_rounding_mode diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 8379491c9ab..a3672bad521 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3061,6 +3061,20 @@ expand_cond_len_unop (unsigned icode, rtx *ops) expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len); } +/* Expand unary ops COND_*. */ +void +expand_cond_unop (unsigned icode, rtx *ops) +{ + rtx dest = ops[0]; + rtx mask = ops[1]; + rtx src = ops[2]; + rtx merge = get_else_operand (ops[3]); + rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode); + + rtx cond_ops[] = {dest, mask, merge, src}; + expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len); +} + /* Expand binary ops COND_LEN_*. */ void expand_cond_len_binop (unsigned icode, rtx *ops) @@ -3076,6 +3090,21 @@ expand_cond_len_binop (unsigned icode, rtx *ops) expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len); } +/* Expand binary ops COND_*. */ +void +expand_cond_binop (unsigned icode, rtx *ops) +{ + rtx dest = ops[0]; + rtx mask = ops[1]; + rtx src1 = ops[2]; + rtx src2 = ops[3]; + rtx merge = get_else_operand (ops[4]); + rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode); + + rtx cond_ops[] = {dest, mask, merge, src1, src2}; + expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len); +} + /* Prepare insn_code for gather_load/scatter_store according to the vector mode and index mode. */ static insn_code @@ -3248,6 +3277,22 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len); } +/* Expand COND_*. */ +void +expand_cond_ternop (unsigned icode, rtx *ops) +{ + rtx dest = ops[0]; + rtx mask = ops[1]; + rtx src1 = ops[2]; + rtx src2 = ops[3]; + rtx src3 = ops[4]; + rtx merge = get_else_operand (ops[5]); + rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode); + + rtx cond_ops[] = {dest, mask, src1, src2, src3, merge}; + expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len); +} + /* Expand reduction operations. Case 1: ops = {scalar_dest, vector_src} Case 2: ops = {scalar_dest, vector_src, mask, vl} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c new file mode 100644 index 00000000000..61da94cbc41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_add, 4, v4qi, +) +DEF_COND_BINOP (cond_add, 8, v8qi, +) +DEF_COND_BINOP (cond_add, 16, v16qi, +) +DEF_COND_BINOP (cond_add, 32, v32qi, +) +DEF_COND_BINOP (cond_add, 64, v64qi, +) +DEF_COND_BINOP (cond_add, 128, v128qi, +) +DEF_COND_BINOP (cond_add, 256, v256qi, +) +DEF_COND_BINOP (cond_add, 512, v512qi, +) +DEF_COND_BINOP (cond_add, 1024, v1024qi, +) +DEF_COND_BINOP (cond_add, 2048, v2048qi, +) +DEF_COND_BINOP (cond_add, 4096, v4096qi, +) + +DEF_COND_BINOP (cond_add, 4, v4hi, +) +DEF_COND_BINOP (cond_add, 8, v8hi, +) +DEF_COND_BINOP (cond_add, 16, v16hi, +) +DEF_COND_BINOP (cond_add, 32, v32hi, +) +DEF_COND_BINOP (cond_add, 64, v64hi, +) +DEF_COND_BINOP (cond_add, 128, v128hi, +) +DEF_COND_BINOP (cond_add, 256, v256hi, +) +DEF_COND_BINOP (cond_add, 512, v512hi, +) +DEF_COND_BINOP (cond_add, 1024, v1024hi, +) +DEF_COND_BINOP (cond_add, 2048, v2048hi, +) + +DEF_COND_BINOP (cond_add, 4, v4si, +) +DEF_COND_BINOP (cond_add, 8, v8si, +) +DEF_COND_BINOP (cond_add, 16, v16si, +) +DEF_COND_BINOP (cond_add, 32, v32si, +) +DEF_COND_BINOP (cond_add, 64, v64si, +) +DEF_COND_BINOP (cond_add, 128, v128si, +) +DEF_COND_BINOP (cond_add, 256, v256si, +) +DEF_COND_BINOP (cond_add, 512, v512si, +) +DEF_COND_BINOP (cond_add, 1024, v1024si, +) + +DEF_COND_BINOP (cond_add, 4, v4di, +) +DEF_COND_BINOP (cond_add, 8, v8di, +) +DEF_COND_BINOP (cond_add, 16, v16di, +) +DEF_COND_BINOP (cond_add, 32, v32di, +) +DEF_COND_BINOP (cond_add, 64, v64di, +) +DEF_COND_BINOP (cond_add, 128, v128di, +) +DEF_COND_BINOP (cond_add, 256, v256di, +) +DEF_COND_BINOP (cond_add, 512, v512di, +) + +DEF_COND_BINOP (cond_add, 4, v4uqi, +) +DEF_COND_BINOP (cond_add, 8, v8uqi, +) +DEF_COND_BINOP (cond_add, 16, v16uqi, +) +DEF_COND_BINOP (cond_add, 32, v32uqi, +) +DEF_COND_BINOP (cond_add, 64, v64uqi, +) +DEF_COND_BINOP (cond_add, 128, v128uqi, +) +DEF_COND_BINOP (cond_add, 256, v256uqi, +) +DEF_COND_BINOP (cond_add, 512, v512uqi, +) +DEF_COND_BINOP (cond_add, 1024, v1024uqi, +) +DEF_COND_BINOP (cond_add, 2048, v2048uqi, +) +DEF_COND_BINOP (cond_add, 4096, v4096uqi, +) + +DEF_COND_BINOP (cond_add, 4, v4uhi, +) +DEF_COND_BINOP (cond_add, 8, v8uhi, +) +DEF_COND_BINOP (cond_add, 16, v16uhi, +) +DEF_COND_BINOP (cond_add, 32, v32uhi, +) +DEF_COND_BINOP (cond_add, 64, v64uhi, +) +DEF_COND_BINOP (cond_add, 128, v128uhi, +) +DEF_COND_BINOP (cond_add, 256, v256uhi, +) +DEF_COND_BINOP (cond_add, 512, v512uhi, +) +DEF_COND_BINOP (cond_add, 1024, v1024uhi, +) +DEF_COND_BINOP (cond_add, 2048, v2048uhi, +) + +DEF_COND_BINOP (cond_add, 4, v4usi, +) +DEF_COND_BINOP (cond_add, 8, v8usi, +) +DEF_COND_BINOP (cond_add, 16, v16usi, +) +DEF_COND_BINOP (cond_add, 32, v32usi, +) +DEF_COND_BINOP (cond_add, 64, v64usi, +) +DEF_COND_BINOP (cond_add, 128, v128usi, +) +DEF_COND_BINOP (cond_add, 256, v256usi, +) +DEF_COND_BINOP (cond_add, 512, v512usi, +) +DEF_COND_BINOP (cond_add, 1024, v1024usi, +) + +DEF_COND_BINOP (cond_add, 4, v4udi, +) +DEF_COND_BINOP (cond_add, 8, v8udi, +) +DEF_COND_BINOP (cond_add, 16, v16udi, +) +DEF_COND_BINOP (cond_add, 32, v32udi, +) +DEF_COND_BINOP (cond_add, 64, v64udi, +) +DEF_COND_BINOP (cond_add, 128, v128udi, +) +DEF_COND_BINOP (cond_add, 256, v256udi, +) +DEF_COND_BINOP (cond_add, 512, v512udi, +) + +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c new file mode 100644 index 00000000000..cb730870211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_add, 4, v4hf, +) +DEF_COND_BINOP (cond_add, 8, v8hf, +) +DEF_COND_BINOP (cond_add, 16, v16hf, +) +DEF_COND_BINOP (cond_add, 32, v32hf, +) +DEF_COND_BINOP (cond_add, 64, v64hf, +) +DEF_COND_BINOP (cond_add, 128, v128hf, +) +DEF_COND_BINOP (cond_add, 256, v256hf, +) +DEF_COND_BINOP (cond_add, 512, v512hf, +) +DEF_COND_BINOP (cond_add, 1024, v1024hf, +) +DEF_COND_BINOP (cond_add, 2048, v2048hf, +) + +DEF_COND_BINOP (cond_add, 4, v4sf, +) +DEF_COND_BINOP (cond_add, 8, v8sf, +) +DEF_COND_BINOP (cond_add, 16, v16sf, +) +DEF_COND_BINOP (cond_add, 32, v32sf, +) +DEF_COND_BINOP (cond_add, 64, v64sf, +) +DEF_COND_BINOP (cond_add, 128, v128sf, +) +DEF_COND_BINOP (cond_add, 256, v256sf, +) +DEF_COND_BINOP (cond_add, 512, v512sf, +) +DEF_COND_BINOP (cond_add, 1024, v1024sf, +) + +DEF_COND_BINOP (cond_add, 4, v4df, +) +DEF_COND_BINOP (cond_add, 8, v8df, +) +DEF_COND_BINOP (cond_add, 16, v16df, +) +DEF_COND_BINOP (cond_add, 32, v32df, +) +DEF_COND_BINOP (cond_add, 64, v64df, +) +DEF_COND_BINOP (cond_add, 128, v128df, +) +DEF_COND_BINOP (cond_add, 256, v256df, +) +DEF_COND_BINOP (cond_add, 512, v512df, +) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c new file mode 100644 index 00000000000..eb8d56a2a1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_and, 4, v4qi, &) +DEF_COND_BINOP (cond_and, 8, v8qi, &) +DEF_COND_BINOP (cond_and, 16, v16qi, &) +DEF_COND_BINOP (cond_and, 32, v32qi, &) +DEF_COND_BINOP (cond_and, 64, v64qi, &) +DEF_COND_BINOP (cond_and, 128, v128qi, &) +DEF_COND_BINOP (cond_and, 256, v256qi, &) +DEF_COND_BINOP (cond_and, 512, v512qi, &) +DEF_COND_BINOP (cond_and, 1024, v1024qi, &) +DEF_COND_BINOP (cond_and, 2048, v2048qi, &) +DEF_COND_BINOP (cond_and, 4096, v4096qi, &) + +DEF_COND_BINOP (cond_and, 4, v4hi, &) +DEF_COND_BINOP (cond_and, 8, v8hi, &) +DEF_COND_BINOP (cond_and, 16, v16hi, &) +DEF_COND_BINOP (cond_and, 32, v32hi, &) +DEF_COND_BINOP (cond_and, 64, v64hi, &) +DEF_COND_BINOP (cond_and, 128, v128hi, &) +DEF_COND_BINOP (cond_and, 256, v256hi, &) +DEF_COND_BINOP (cond_and, 512, v512hi, &) +DEF_COND_BINOP (cond_and, 1024, v1024hi, &) +DEF_COND_BINOP (cond_and, 2048, v2048hi, &) + +DEF_COND_BINOP (cond_and, 4, v4si, &) +DEF_COND_BINOP (cond_and, 8, v8si, &) +DEF_COND_BINOP (cond_and, 16, v16si, &) +DEF_COND_BINOP (cond_and, 32, v32si, &) +DEF_COND_BINOP (cond_and, 64, v64si, &) +DEF_COND_BINOP (cond_and, 128, v128si, &) +DEF_COND_BINOP (cond_and, 256, v256si, &) +DEF_COND_BINOP (cond_and, 512, v512si, &) +DEF_COND_BINOP (cond_and, 1024, v1024si, &) + +DEF_COND_BINOP (cond_and, 4, v4di, &) +DEF_COND_BINOP (cond_and, 8, v8di, &) +DEF_COND_BINOP (cond_and, 16, v16di, &) +DEF_COND_BINOP (cond_and, 32, v32di, &) +DEF_COND_BINOP (cond_and, 64, v64di, &) +DEF_COND_BINOP (cond_and, 128, v128di, &) +DEF_COND_BINOP (cond_and, 256, v256di, &) +DEF_COND_BINOP (cond_and, 512, v512di, &) + +DEF_COND_BINOP (cond_and, 4, v4uqi, &) +DEF_COND_BINOP (cond_and, 8, v8uqi, &) +DEF_COND_BINOP (cond_and, 16, v16uqi, &) +DEF_COND_BINOP (cond_and, 32, v32uqi, &) +DEF_COND_BINOP (cond_and, 64, v64uqi, &) +DEF_COND_BINOP (cond_and, 128, v128uqi, &) +DEF_COND_BINOP (cond_and, 256, v256uqi, &) +DEF_COND_BINOP (cond_and, 512, v512uqi, &) +DEF_COND_BINOP (cond_and, 1024, v1024uqi, &) +DEF_COND_BINOP (cond_and, 2048, v2048uqi, &) +DEF_COND_BINOP (cond_and, 4096, v4096uqi, &) + +DEF_COND_BINOP (cond_and, 4, v4uhi, &) +DEF_COND_BINOP (cond_and, 8, v8uhi, &) +DEF_COND_BINOP (cond_and, 16, v16uhi, &) +DEF_COND_BINOP (cond_and, 32, v32uhi, &) +DEF_COND_BINOP (cond_and, 64, v64uhi, &) +DEF_COND_BINOP (cond_and, 128, v128uhi, &) +DEF_COND_BINOP (cond_and, 256, v256uhi, &) +DEF_COND_BINOP (cond_and, 512, v512uhi, &) +DEF_COND_BINOP (cond_and, 1024, v1024uhi, &) +DEF_COND_BINOP (cond_and, 2048, v2048uhi, &) + +DEF_COND_BINOP (cond_and, 4, v4usi, &) +DEF_COND_BINOP (cond_and, 8, v8usi, &) +DEF_COND_BINOP (cond_and, 16, v16usi, &) +DEF_COND_BINOP (cond_and, 32, v32usi, &) +DEF_COND_BINOP (cond_and, 64, v64usi, &) +DEF_COND_BINOP (cond_and, 128, v128usi, &) +DEF_COND_BINOP (cond_and, 256, v256usi, &) +DEF_COND_BINOP (cond_and, 512, v512usi, &) +DEF_COND_BINOP (cond_and, 1024, v1024usi, &) + +DEF_COND_BINOP (cond_and, 4, v4udi, &) +DEF_COND_BINOP (cond_and, 8, v8udi, &) +DEF_COND_BINOP (cond_and, 16, v16udi, &) +DEF_COND_BINOP (cond_and, 32, v32udi, &) +DEF_COND_BINOP (cond_and, 64, v64udi, &) +DEF_COND_BINOP (cond_and, 128, v128udi, &) +DEF_COND_BINOP (cond_and, 256, v256udi, &) +DEF_COND_BINOP (cond_and, 512, v512udi, &) + +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c new file mode 100644 index 00000000000..373ff00f95b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_div, 4, v4si, /) +DEF_COND_BINOP (cond_div, 8, v8si, /) +DEF_COND_BINOP (cond_div, 16, v16si, /) +DEF_COND_BINOP (cond_div, 32, v32si, /) +DEF_COND_BINOP (cond_div, 64, v64si, /) +DEF_COND_BINOP (cond_div, 128, v128si, /) +DEF_COND_BINOP (cond_div, 256, v256si, /) +DEF_COND_BINOP (cond_div, 512, v512si, /) +DEF_COND_BINOP (cond_div, 1024, v1024si, /) + +DEF_COND_BINOP (cond_div, 4, v4di, /) +DEF_COND_BINOP (cond_div, 8, v8di, /) +DEF_COND_BINOP (cond_div, 16, v16di, /) +DEF_COND_BINOP (cond_div, 32, v32di, /) +DEF_COND_BINOP (cond_div, 64, v64di, /) +DEF_COND_BINOP (cond_div, 128, v128di, /) +DEF_COND_BINOP (cond_div, 256, v256di, /) +DEF_COND_BINOP (cond_div, 512, v512di, /) + +DEF_COND_BINOP (cond_div, 4, v4usi, /) +DEF_COND_BINOP (cond_div, 8, v8usi, /) +DEF_COND_BINOP (cond_div, 16, v16usi, /) +DEF_COND_BINOP (cond_div, 32, v32usi, /) +DEF_COND_BINOP (cond_div, 64, v64usi, /) +DEF_COND_BINOP (cond_div, 128, v128usi, /) +DEF_COND_BINOP (cond_div, 256, v256usi, /) +DEF_COND_BINOP (cond_div, 512, v512usi, /) +DEF_COND_BINOP (cond_div, 1024, v1024usi, /) + +DEF_COND_BINOP (cond_div, 4, v4udi, /) +DEF_COND_BINOP (cond_div, 8, v8udi, /) +DEF_COND_BINOP (cond_div, 16, v16udi, /) +DEF_COND_BINOP (cond_div, 32, v32udi, /) +DEF_COND_BINOP (cond_div, 64, v64udi, /) +DEF_COND_BINOP (cond_div, 128, v128udi, /) +DEF_COND_BINOP (cond_div, 256, v256udi, /) +DEF_COND_BINOP (cond_div, 512, v512udi, /) + +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 34 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c new file mode 100644 index 00000000000..fac75ef0775 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_div, 4, v4hf, /) +DEF_COND_BINOP (cond_div, 8, v8hf, /) +DEF_COND_BINOP (cond_div, 16, v16hf, /) +DEF_COND_BINOP (cond_div, 32, v32hf, /) +DEF_COND_BINOP (cond_div, 64, v64hf, /) +DEF_COND_BINOP (cond_div, 128, v128hf, /) +DEF_COND_BINOP (cond_div, 256, v256hf, /) +DEF_COND_BINOP (cond_div, 512, v512hf, /) +DEF_COND_BINOP (cond_div, 1024, v1024hf, /) +DEF_COND_BINOP (cond_div, 2048, v2048hf, /) + +DEF_COND_BINOP (cond_div, 4, v4sf, /) +DEF_COND_BINOP (cond_div, 8, v8sf, /) +DEF_COND_BINOP (cond_div, 16, v16sf, /) +DEF_COND_BINOP (cond_div, 32, v32sf, /) +DEF_COND_BINOP (cond_div, 64, v64sf, /) +DEF_COND_BINOP (cond_div, 128, v128sf, /) +DEF_COND_BINOP (cond_div, 256, v256sf, /) +DEF_COND_BINOP (cond_div, 512, v512sf, /) +DEF_COND_BINOP (cond_div, 1024, v1024sf, /) + +DEF_COND_BINOP (cond_div, 4, v4df, /) +DEF_COND_BINOP (cond_div, 8, v8df, /) +DEF_COND_BINOP (cond_div, 16, v16df, /) +DEF_COND_BINOP (cond_div, 32, v32df, /) +DEF_COND_BINOP (cond_div, 64, v64df, /) +DEF_COND_BINOP (cond_div, 128, v128df, /) +DEF_COND_BINOP (cond_div, 256, v256df, /) +DEF_COND_BINOP (cond_div, 512, v512df, /) + +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c new file mode 100644 index 00000000000..54d2f0721f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FMA_VV (cond_fma, 4, v4qi) +DEF_COND_FMA_VV (cond_fma, 8, v8qi) +DEF_COND_FMA_VV (cond_fma, 16, v16qi) +DEF_COND_FMA_VV (cond_fma, 32, v32qi) +DEF_COND_FMA_VV (cond_fma, 64, v64qi) +DEF_COND_FMA_VV (cond_fma, 128, v128qi) +DEF_COND_FMA_VV (cond_fma, 256, v256qi) +DEF_COND_FMA_VV (cond_fma, 512, v512qi) +DEF_COND_FMA_VV (cond_fma, 1024, v1024qi) +DEF_COND_FMA_VV (cond_fma, 2048, v2048qi) +DEF_COND_FMA_VV (cond_fma, 4096, v4096qi) + +DEF_COND_FMA_VV (cond_fma, 4, v4hi) +DEF_COND_FMA_VV (cond_fma, 8, v8hi) +DEF_COND_FMA_VV (cond_fma, 16, v16hi) +DEF_COND_FMA_VV (cond_fma, 32, v32hi) +DEF_COND_FMA_VV (cond_fma, 64, v64hi) +DEF_COND_FMA_VV (cond_fma, 128, v128hi) +DEF_COND_FMA_VV (cond_fma, 256, v256hi) +DEF_COND_FMA_VV (cond_fma, 512, v512hi) +DEF_COND_FMA_VV (cond_fma, 1024, v1024hi) +DEF_COND_FMA_VV (cond_fma, 2048, v2048hi) + +DEF_COND_FMA_VV (cond_fma, 4, v4si) +DEF_COND_FMA_VV (cond_fma, 8, v8si) +DEF_COND_FMA_VV (cond_fma, 16, v16si) +DEF_COND_FMA_VV (cond_fma, 32, v32si) +DEF_COND_FMA_VV (cond_fma, 64, v64si) +DEF_COND_FMA_VV (cond_fma, 128, v128si) +DEF_COND_FMA_VV (cond_fma, 256, v256si) +DEF_COND_FMA_VV (cond_fma, 512, v512si) +DEF_COND_FMA_VV (cond_fma, 1024, v1024si) + +DEF_COND_FMA_VV (cond_fma, 4, v4di) +DEF_COND_FMA_VV (cond_fma, 8, v8di) +DEF_COND_FMA_VV (cond_fma, 16, v16di) +DEF_COND_FMA_VV (cond_fma, 32, v32di) +DEF_COND_FMA_VV (cond_fma, 64, v64di) +DEF_COND_FMA_VV (cond_fma, 128, v128di) +DEF_COND_FMA_VV (cond_fma, 256, v256di) +DEF_COND_FMA_VV (cond_fma, 512, v512di) + +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c new file mode 100644 index 00000000000..145f81fa5c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FMA_VV (cond_fma, 4, v4hf) +DEF_COND_FMA_VV (cond_fma, 8, v8hf) +DEF_COND_FMA_VV (cond_fma, 16, v16hf) +DEF_COND_FMA_VV (cond_fma, 32, v32hf) +DEF_COND_FMA_VV (cond_fma, 64, v64hf) +DEF_COND_FMA_VV (cond_fma, 128, v128hf) +DEF_COND_FMA_VV (cond_fma, 256, v256hf) +DEF_COND_FMA_VV (cond_fma, 512, v512hf) +DEF_COND_FMA_VV (cond_fma, 1024, v1024hf) +DEF_COND_FMA_VV (cond_fma, 2048, v2048hf) + +DEF_COND_FMA_VV (cond_fma, 4, v4sf) +DEF_COND_FMA_VV (cond_fma, 8, v8sf) +DEF_COND_FMA_VV (cond_fma, 16, v16sf) +DEF_COND_FMA_VV (cond_fma, 32, v32sf) +DEF_COND_FMA_VV (cond_fma, 64, v64sf) +DEF_COND_FMA_VV (cond_fma, 128, v128sf) +DEF_COND_FMA_VV (cond_fma, 256, v256sf) +DEF_COND_FMA_VV (cond_fma, 512, v512sf) +DEF_COND_FMA_VV (cond_fma, 1024, v1024sf) + +DEF_COND_FMA_VV (cond_fma, 4, v4df) +DEF_COND_FMA_VV (cond_fma, 8, v8df) +DEF_COND_FMA_VV (cond_fma, 16, v16df) +DEF_COND_FMA_VV (cond_fma, 32, v32df) +DEF_COND_FMA_VV (cond_fma, 64, v64df) +DEF_COND_FMA_VV (cond_fma, 128, v128df) +DEF_COND_FMA_VV (cond_fma, 256, v256df) +DEF_COND_FMA_VV (cond_fma, 512, v512df) + +/* { dg-final { scan-assembler-times {vfma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c new file mode 100644 index 00000000000..bfed1dbec02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FMS_VV (cond_fms, 4, v4hf) +DEF_COND_FMS_VV (cond_fms, 8, v8hf) +DEF_COND_FMS_VV (cond_fms, 16, v16hf) +DEF_COND_FMS_VV (cond_fms, 32, v32hf) +DEF_COND_FMS_VV (cond_fms, 64, v64hf) +DEF_COND_FMS_VV (cond_fms, 128, v128hf) +DEF_COND_FMS_VV (cond_fms, 256, v256hf) +DEF_COND_FMS_VV (cond_fms, 512, v512hf) +DEF_COND_FMS_VV (cond_fms, 1024, v1024hf) +DEF_COND_FMS_VV (cond_fms, 2048, v2048hf) + +DEF_COND_FMS_VV (cond_fms, 4, v4sf) +DEF_COND_FMS_VV (cond_fms, 8, v8sf) +DEF_COND_FMS_VV (cond_fms, 16, v16sf) +DEF_COND_FMS_VV (cond_fms, 32, v32sf) +DEF_COND_FMS_VV (cond_fms, 64, v64sf) +DEF_COND_FMS_VV (cond_fms, 128, v128sf) +DEF_COND_FMS_VV (cond_fms, 256, v256sf) +DEF_COND_FMS_VV (cond_fms, 512, v512sf) +DEF_COND_FMS_VV (cond_fms, 1024, v1024sf) + +DEF_COND_FMS_VV (cond_fms, 4, v4df) +DEF_COND_FMS_VV (cond_fms, 8, v8df) +DEF_COND_FMS_VV (cond_fms, 16, v16df) +DEF_COND_FMS_VV (cond_fms, 32, v32df) +DEF_COND_FMS_VV (cond_fms, 64, v64df) +DEF_COND_FMS_VV (cond_fms, 128, v128df) +DEF_COND_FMS_VV (cond_fms, 256, v256df) +DEF_COND_FMS_VV (cond_fms, 512, v512df) + +/* { dg-final { scan-assembler-times {vfms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c new file mode 100644 index 00000000000..5871c71fdbf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FNMA_VV (cond_fnma, 4, v4qi) +DEF_COND_FNMA_VV (cond_fnma, 8, v8qi) +DEF_COND_FNMA_VV (cond_fnma, 16, v16qi) +DEF_COND_FNMA_VV (cond_fnma, 32, v32qi) +DEF_COND_FNMA_VV (cond_fnma, 64, v64qi) +DEF_COND_FNMA_VV (cond_fnma, 128, v128qi) +DEF_COND_FNMA_VV (cond_fnma, 256, v256qi) +DEF_COND_FNMA_VV (cond_fnma, 512, v512qi) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024qi) +DEF_COND_FNMA_VV (cond_fnma, 2048, v2048qi) +DEF_COND_FNMA_VV (cond_fnma, 4096, v4096qi) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4hi) +DEF_COND_FNMA_VV (cond_fnma, 8, v8hi) +DEF_COND_FNMA_VV (cond_fnma, 16, v16hi) +DEF_COND_FNMA_VV (cond_fnma, 32, v32hi) +DEF_COND_FNMA_VV (cond_fnma, 64, v64hi) +DEF_COND_FNMA_VV (cond_fnma, 128, v128hi) +DEF_COND_FNMA_VV (cond_fnma, 256, v256hi) +DEF_COND_FNMA_VV (cond_fnma, 512, v512hi) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024hi) +DEF_COND_FNMA_VV (cond_fnma, 2048, v2048hi) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4si) +DEF_COND_FNMA_VV (cond_fnma, 8, v8si) +DEF_COND_FNMA_VV (cond_fnma, 16, v16si) +DEF_COND_FNMA_VV (cond_fnma, 32, v32si) +DEF_COND_FNMA_VV (cond_fnma, 64, v64si) +DEF_COND_FNMA_VV (cond_fnma, 128, v128si) +DEF_COND_FNMA_VV (cond_fnma, 256, v256si) +DEF_COND_FNMA_VV (cond_fnma, 512, v512si) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024si) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4di) +DEF_COND_FNMA_VV (cond_fnma, 8, v8di) +DEF_COND_FNMA_VV (cond_fnma, 16, v16di) +DEF_COND_FNMA_VV (cond_fnma, 32, v32di) +DEF_COND_FNMA_VV (cond_fnma, 64, v64di) +DEF_COND_FNMA_VV (cond_fnma, 128, v128di) +DEF_COND_FNMA_VV (cond_fnma, 256, v256di) +DEF_COND_FNMA_VV (cond_fnma, 512, v512di) + +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c new file mode 100644 index 00000000000..f91039aa366 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FNMA_VV (cond_fnma, 4, v4hf) +DEF_COND_FNMA_VV (cond_fnma, 8, v8hf) +DEF_COND_FNMA_VV (cond_fnma, 16, v16hf) +DEF_COND_FNMA_VV (cond_fnma, 32, v32hf) +DEF_COND_FNMA_VV (cond_fnma, 64, v64hf) +DEF_COND_FNMA_VV (cond_fnma, 128, v128hf) +DEF_COND_FNMA_VV (cond_fnma, 256, v256hf) +DEF_COND_FNMA_VV (cond_fnma, 512, v512hf) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024hf) +DEF_COND_FNMA_VV (cond_fnma, 2048, v2048hf) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4sf) +DEF_COND_FNMA_VV (cond_fnma, 8, v8sf) +DEF_COND_FNMA_VV (cond_fnma, 16, v16sf) +DEF_COND_FNMA_VV (cond_fnma, 32, v32sf) +DEF_COND_FNMA_VV (cond_fnma, 64, v64sf) +DEF_COND_FNMA_VV (cond_fnma, 128, v128sf) +DEF_COND_FNMA_VV (cond_fnma, 256, v256sf) +DEF_COND_FNMA_VV (cond_fnma, 512, v512sf) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024sf) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4df) +DEF_COND_FNMA_VV (cond_fnma, 8, v8df) +DEF_COND_FNMA_VV (cond_fnma, 16, v16df) +DEF_COND_FNMA_VV (cond_fnma, 32, v32df) +DEF_COND_FNMA_VV (cond_fnma, 64, v64df) +DEF_COND_FNMA_VV (cond_fnma, 128, v128df) +DEF_COND_FNMA_VV (cond_fnma, 256, v256df) +DEF_COND_FNMA_VV (cond_fnma, 512, v512df) + +/* { dg-final { scan-assembler-times {vfnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c new file mode 100644 index 00000000000..59fae9b4788 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FNMS_VV (cond_fnms, 4, v4hf) +DEF_COND_FNMS_VV (cond_fnms, 8, v8hf) +DEF_COND_FNMS_VV (cond_fnms, 16, v16hf) +DEF_COND_FNMS_VV (cond_fnms, 32, v32hf) +DEF_COND_FNMS_VV (cond_fnms, 64, v64hf) +DEF_COND_FNMS_VV (cond_fnms, 128, v128hf) +DEF_COND_FNMS_VV (cond_fnms, 256, v256hf) +DEF_COND_FNMS_VV (cond_fnms, 512, v512hf) +DEF_COND_FNMS_VV (cond_fnms, 1024, v1024hf) +DEF_COND_FNMS_VV (cond_fnms, 2048, v2048hf) + +DEF_COND_FNMS_VV (cond_fnms, 4, v4sf) +DEF_COND_FNMS_VV (cond_fnms, 8, v8sf) +DEF_COND_FNMS_VV (cond_fnms, 16, v16sf) +DEF_COND_FNMS_VV (cond_fnms, 32, v32sf) +DEF_COND_FNMS_VV (cond_fnms, 64, v64sf) +DEF_COND_FNMS_VV (cond_fnms, 128, v128sf) +DEF_COND_FNMS_VV (cond_fnms, 256, v256sf) +DEF_COND_FNMS_VV (cond_fnms, 512, v512sf) +DEF_COND_FNMS_VV (cond_fnms, 1024, v1024sf) + +DEF_COND_FNMS_VV (cond_fnms, 4, v4df) +DEF_COND_FNMS_VV (cond_fnms, 8, v8df) +DEF_COND_FNMS_VV (cond_fnms, 16, v16df) +DEF_COND_FNMS_VV (cond_fnms, 32, v32df) +DEF_COND_FNMS_VV (cond_fnms, 64, v64df) +DEF_COND_FNMS_VV (cond_fnms, 128, v128df) +DEF_COND_FNMS_VV (cond_fnms, 256, v256df) +DEF_COND_FNMS_VV (cond_fnms, 512, v512df) + +/* { dg-final { scan-assembler-times {vfnma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c new file mode 100644 index 00000000000..2c30854033e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_ior, 4, v4qi, |) +DEF_COND_BINOP (cond_ior, 8, v8qi, |) +DEF_COND_BINOP (cond_ior, 16, v16qi, |) +DEF_COND_BINOP (cond_ior, 32, v32qi, |) +DEF_COND_BINOP (cond_ior, 64, v64qi, |) +DEF_COND_BINOP (cond_ior, 128, v128qi, |) +DEF_COND_BINOP (cond_ior, 256, v256qi, |) +DEF_COND_BINOP (cond_ior, 512, v512qi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024qi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048qi, |) +DEF_COND_BINOP (cond_ior, 4096, v4096qi, |) + +DEF_COND_BINOP (cond_ior, 4, v4hi, |) +DEF_COND_BINOP (cond_ior, 8, v8hi, |) +DEF_COND_BINOP (cond_ior, 16, v16hi, |) +DEF_COND_BINOP (cond_ior, 32, v32hi, |) +DEF_COND_BINOP (cond_ior, 64, v64hi, |) +DEF_COND_BINOP (cond_ior, 128, v128hi, |) +DEF_COND_BINOP (cond_ior, 256, v256hi, |) +DEF_COND_BINOP (cond_ior, 512, v512hi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024hi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048hi, |) + +DEF_COND_BINOP (cond_ior, 4, v4si, |) +DEF_COND_BINOP (cond_ior, 8, v8si, |) +DEF_COND_BINOP (cond_ior, 16, v16si, |) +DEF_COND_BINOP (cond_ior, 32, v32si, |) +DEF_COND_BINOP (cond_ior, 64, v64si, |) +DEF_COND_BINOP (cond_ior, 128, v128si, |) +DEF_COND_BINOP (cond_ior, 256, v256si, |) +DEF_COND_BINOP (cond_ior, 512, v512si, |) +DEF_COND_BINOP (cond_ior, 1024, v1024si, |) + +DEF_COND_BINOP (cond_ior, 4, v4di, |) +DEF_COND_BINOP (cond_ior, 8, v8di, |) +DEF_COND_BINOP (cond_ior, 16, v16di, |) +DEF_COND_BINOP (cond_ior, 32, v32di, |) +DEF_COND_BINOP (cond_ior, 64, v64di, |) +DEF_COND_BINOP (cond_ior, 128, v128di, |) +DEF_COND_BINOP (cond_ior, 256, v256di, |) +DEF_COND_BINOP (cond_ior, 512, v512di, |) + +DEF_COND_BINOP (cond_ior, 4, v4uqi, |) +DEF_COND_BINOP (cond_ior, 8, v8uqi, |) +DEF_COND_BINOP (cond_ior, 16, v16uqi, |) +DEF_COND_BINOP (cond_ior, 32, v32uqi, |) +DEF_COND_BINOP (cond_ior, 64, v64uqi, |) +DEF_COND_BINOP (cond_ior, 128, v128uqi, |) +DEF_COND_BINOP (cond_ior, 256, v256uqi, |) +DEF_COND_BINOP (cond_ior, 512, v512uqi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024uqi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048uqi, |) +DEF_COND_BINOP (cond_ior, 4096, v4096uqi, |) + +DEF_COND_BINOP (cond_ior, 4, v4uhi, |) +DEF_COND_BINOP (cond_ior, 8, v8uhi, |) +DEF_COND_BINOP (cond_ior, 16, v16uhi, |) +DEF_COND_BINOP (cond_ior, 32, v32uhi, |) +DEF_COND_BINOP (cond_ior, 64, v64uhi, |) +DEF_COND_BINOP (cond_ior, 128, v128uhi, |) +DEF_COND_BINOP (cond_ior, 256, v256uhi, |) +DEF_COND_BINOP (cond_ior, 512, v512uhi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024uhi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048uhi, |) + +DEF_COND_BINOP (cond_ior, 4, v4usi, |) +DEF_COND_BINOP (cond_ior, 8, v8usi, |) +DEF_COND_BINOP (cond_ior, 16, v16usi, |) +DEF_COND_BINOP (cond_ior, 32, v32usi, |) +DEF_COND_BINOP (cond_ior, 64, v64usi, |) +DEF_COND_BINOP (cond_ior, 128, v128usi, |) +DEF_COND_BINOP (cond_ior, 256, v256usi, |) +DEF_COND_BINOP (cond_ior, 512, v512usi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024usi, |) + +DEF_COND_BINOP (cond_ior, 4, v4udi, |) +DEF_COND_BINOP (cond_ior, 8, v8udi, |) +DEF_COND_BINOP (cond_ior, 16, v16udi, |) +DEF_COND_BINOP (cond_ior, 32, v32udi, |) +DEF_COND_BINOP (cond_ior, 64, v64udi, |) +DEF_COND_BINOP (cond_ior, 128, v128udi, |) +DEF_COND_BINOP (cond_ior, 256, v256udi, |) +DEF_COND_BINOP (cond_ior, 512, v512udi, |) + +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c new file mode 100644 index 00000000000..60e0f9391d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_max, 4, v4qi, >=) +DEF_COND_MINMAX (cond_max, 8, v8qi, >=) +DEF_COND_MINMAX (cond_max, 16, v16qi, >=) +DEF_COND_MINMAX (cond_max, 32, v32qi, >=) +DEF_COND_MINMAX (cond_max, 64, v64qi, >=) +DEF_COND_MINMAX (cond_max, 128, v128qi, >=) +DEF_COND_MINMAX (cond_max, 256, v256qi, >=) +DEF_COND_MINMAX (cond_max, 512, v512qi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024qi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048qi, >=) +DEF_COND_MINMAX (cond_max, 4096, v4096qi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4hi, >=) +DEF_COND_MINMAX (cond_max, 8, v8hi, >=) +DEF_COND_MINMAX (cond_max, 16, v16hi, >=) +DEF_COND_MINMAX (cond_max, 32, v32hi, >=) +DEF_COND_MINMAX (cond_max, 64, v64hi, >=) +DEF_COND_MINMAX (cond_max, 128, v128hi, >=) +DEF_COND_MINMAX (cond_max, 256, v256hi, >=) +DEF_COND_MINMAX (cond_max, 512, v512hi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024hi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048hi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4si, >=) +DEF_COND_MINMAX (cond_max, 8, v8si, >=) +DEF_COND_MINMAX (cond_max, 16, v16si, >=) +DEF_COND_MINMAX (cond_max, 32, v32si, >=) +DEF_COND_MINMAX (cond_max, 64, v64si, >=) +DEF_COND_MINMAX (cond_max, 128, v128si, >=) +DEF_COND_MINMAX (cond_max, 256, v256si, >=) +DEF_COND_MINMAX (cond_max, 512, v512si, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024si, >=) + +DEF_COND_MINMAX (cond_max, 4, v4di, >=) +DEF_COND_MINMAX (cond_max, 8, v8di, >=) +DEF_COND_MINMAX (cond_max, 16, v16di, >=) +DEF_COND_MINMAX (cond_max, 32, v32di, >=) +DEF_COND_MINMAX (cond_max, 64, v64di, >=) +DEF_COND_MINMAX (cond_max, 128, v128di, >=) +DEF_COND_MINMAX (cond_max, 256, v256di, >=) +DEF_COND_MINMAX (cond_max, 512, v512di, >=) + +DEF_COND_MINMAX (cond_max, 4, v4uqi, >=) +DEF_COND_MINMAX (cond_max, 8, v8uqi, >=) +DEF_COND_MINMAX (cond_max, 16, v16uqi, >=) +DEF_COND_MINMAX (cond_max, 32, v32uqi, >=) +DEF_COND_MINMAX (cond_max, 64, v64uqi, >=) +DEF_COND_MINMAX (cond_max, 128, v128uqi, >=) +DEF_COND_MINMAX (cond_max, 256, v256uqi, >=) +DEF_COND_MINMAX (cond_max, 512, v512uqi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024uqi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048uqi, >=) +DEF_COND_MINMAX (cond_max, 4096, v4096uqi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4uhi, >=) +DEF_COND_MINMAX (cond_max, 8, v8uhi, >=) +DEF_COND_MINMAX (cond_max, 16, v16uhi, >=) +DEF_COND_MINMAX (cond_max, 32, v32uhi, >=) +DEF_COND_MINMAX (cond_max, 64, v64uhi, >=) +DEF_COND_MINMAX (cond_max, 128, v128uhi, >=) +DEF_COND_MINMAX (cond_max, 256, v256uhi, >=) +DEF_COND_MINMAX (cond_max, 512, v512uhi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024uhi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048uhi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4usi, >=) +DEF_COND_MINMAX (cond_max, 8, v8usi, >=) +DEF_COND_MINMAX (cond_max, 16, v16usi, >=) +DEF_COND_MINMAX (cond_max, 32, v32usi, >=) +DEF_COND_MINMAX (cond_max, 64, v64usi, >=) +DEF_COND_MINMAX (cond_max, 128, v128usi, >=) +DEF_COND_MINMAX (cond_max, 256, v256usi, >=) +DEF_COND_MINMAX (cond_max, 512, v512usi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024usi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4udi, >=) +DEF_COND_MINMAX (cond_max, 8, v8udi, >=) +DEF_COND_MINMAX (cond_max, 16, v16udi, >=) +DEF_COND_MINMAX (cond_max, 32, v32udi, >=) +DEF_COND_MINMAX (cond_max, 64, v64udi, >=) +DEF_COND_MINMAX (cond_max, 128, v128udi, >=) +DEF_COND_MINMAX (cond_max, 256, v256udi, >=) +DEF_COND_MINMAX (cond_max, 512, v512udi, >=) + +/* { dg-final { scan-assembler-times {vmaxu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c new file mode 100644 index 00000000000..f8db2925b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_max, 4, v4hf, >=) +DEF_COND_MINMAX (cond_max, 8, v8hf, >=) +DEF_COND_MINMAX (cond_max, 16, v16hf, >=) +DEF_COND_MINMAX (cond_max, 32, v32hf, >=) +DEF_COND_MINMAX (cond_max, 64, v64hf, >=) +DEF_COND_MINMAX (cond_max, 128, v128hf, >=) +DEF_COND_MINMAX (cond_max, 256, v256hf, >=) +DEF_COND_MINMAX (cond_max, 512, v512hf, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024hf, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048hf, >=) + +DEF_COND_MINMAX (cond_max, 4, v4sf, >=) +DEF_COND_MINMAX (cond_max, 8, v8sf, >=) +DEF_COND_MINMAX (cond_max, 16, v16sf, >=) +DEF_COND_MINMAX (cond_max, 32, v32sf, >=) +DEF_COND_MINMAX (cond_max, 64, v64sf, >=) +DEF_COND_MINMAX (cond_max, 128, v128sf, >=) +DEF_COND_MINMAX (cond_max, 256, v256sf, >=) +DEF_COND_MINMAX (cond_max, 512, v512sf, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024sf, >=) + +DEF_COND_MINMAX (cond_max, 4, v4df, >=) +DEF_COND_MINMAX (cond_max, 8, v8df, >=) +DEF_COND_MINMAX (cond_max, 16, v16df, >=) +DEF_COND_MINMAX (cond_max, 32, v32df, >=) +DEF_COND_MINMAX (cond_max, 64, v64df, >=) +DEF_COND_MINMAX (cond_max, 128, v128df, >=) +DEF_COND_MINMAX (cond_max, 256, v256df, >=) +DEF_COND_MINMAX (cond_max, 512, v512df, >=) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c new file mode 100644 index 00000000000..2a13c254e7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_min, 4, v4qi, <=) +DEF_COND_MINMAX (cond_min, 8, v8qi, <=) +DEF_COND_MINMAX (cond_min, 16, v16qi, <=) +DEF_COND_MINMAX (cond_min, 32, v32qi, <=) +DEF_COND_MINMAX (cond_min, 64, v64qi, <=) +DEF_COND_MINMAX (cond_min, 128, v128qi, <=) +DEF_COND_MINMAX (cond_min, 256, v256qi, <=) +DEF_COND_MINMAX (cond_min, 512, v512qi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024qi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048qi, <=) +DEF_COND_MINMAX (cond_min, 4096, v4096qi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4hi, <=) +DEF_COND_MINMAX (cond_min, 8, v8hi, <=) +DEF_COND_MINMAX (cond_min, 16, v16hi, <=) +DEF_COND_MINMAX (cond_min, 32, v32hi, <=) +DEF_COND_MINMAX (cond_min, 64, v64hi, <=) +DEF_COND_MINMAX (cond_min, 128, v128hi, <=) +DEF_COND_MINMAX (cond_min, 256, v256hi, <=) +DEF_COND_MINMAX (cond_min, 512, v512hi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024hi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048hi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4si, <=) +DEF_COND_MINMAX (cond_min, 8, v8si, <=) +DEF_COND_MINMAX (cond_min, 16, v16si, <=) +DEF_COND_MINMAX (cond_min, 32, v32si, <=) +DEF_COND_MINMAX (cond_min, 64, v64si, <=) +DEF_COND_MINMAX (cond_min, 128, v128si, <=) +DEF_COND_MINMAX (cond_min, 256, v256si, <=) +DEF_COND_MINMAX (cond_min, 512, v512si, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024si, <=) + +DEF_COND_MINMAX (cond_min, 4, v4di, <=) +DEF_COND_MINMAX (cond_min, 8, v8di, <=) +DEF_COND_MINMAX (cond_min, 16, v16di, <=) +DEF_COND_MINMAX (cond_min, 32, v32di, <=) +DEF_COND_MINMAX (cond_min, 64, v64di, <=) +DEF_COND_MINMAX (cond_min, 128, v128di, <=) +DEF_COND_MINMAX (cond_min, 256, v256di, <=) +DEF_COND_MINMAX (cond_min, 512, v512di, <=) + +DEF_COND_MINMAX (cond_min, 4, v4uqi, <=) +DEF_COND_MINMAX (cond_min, 8, v8uqi, <=) +DEF_COND_MINMAX (cond_min, 16, v16uqi, <=) +DEF_COND_MINMAX (cond_min, 32, v32uqi, <=) +DEF_COND_MINMAX (cond_min, 64, v64uqi, <=) +DEF_COND_MINMAX (cond_min, 128, v128uqi, <=) +DEF_COND_MINMAX (cond_min, 256, v256uqi, <=) +DEF_COND_MINMAX (cond_min, 512, v512uqi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024uqi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048uqi, <=) +DEF_COND_MINMAX (cond_min, 4096, v4096uqi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4uhi, <=) +DEF_COND_MINMAX (cond_min, 8, v8uhi, <=) +DEF_COND_MINMAX (cond_min, 16, v16uhi, <=) +DEF_COND_MINMAX (cond_min, 32, v32uhi, <=) +DEF_COND_MINMAX (cond_min, 64, v64uhi, <=) +DEF_COND_MINMAX (cond_min, 128, v128uhi, <=) +DEF_COND_MINMAX (cond_min, 256, v256uhi, <=) +DEF_COND_MINMAX (cond_min, 512, v512uhi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024uhi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048uhi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4usi, <=) +DEF_COND_MINMAX (cond_min, 8, v8usi, <=) +DEF_COND_MINMAX (cond_min, 16, v16usi, <=) +DEF_COND_MINMAX (cond_min, 32, v32usi, <=) +DEF_COND_MINMAX (cond_min, 64, v64usi, <=) +DEF_COND_MINMAX (cond_min, 128, v128usi, <=) +DEF_COND_MINMAX (cond_min, 256, v256usi, <=) +DEF_COND_MINMAX (cond_min, 512, v512usi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024usi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4udi, <=) +DEF_COND_MINMAX (cond_min, 8, v8udi, <=) +DEF_COND_MINMAX (cond_min, 16, v16udi, <=) +DEF_COND_MINMAX (cond_min, 32, v32udi, <=) +DEF_COND_MINMAX (cond_min, 64, v64udi, <=) +DEF_COND_MINMAX (cond_min, 128, v128udi, <=) +DEF_COND_MINMAX (cond_min, 256, v256udi, <=) +DEF_COND_MINMAX (cond_min, 512, v512udi, <=) + +/* { dg-final { scan-assembler-times {vminu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c new file mode 100644 index 00000000000..0ae82085b1b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_min, 4, v4hf, <=) +DEF_COND_MINMAX (cond_min, 8, v8hf, <=) +DEF_COND_MINMAX (cond_min, 16, v16hf, <=) +DEF_COND_MINMAX (cond_min, 32, v32hf, <=) +DEF_COND_MINMAX (cond_min, 64, v64hf, <=) +DEF_COND_MINMAX (cond_min, 128, v128hf, <=) +DEF_COND_MINMAX (cond_min, 256, v256hf, <=) +DEF_COND_MINMAX (cond_min, 512, v512hf, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024hf, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048hf, <=) + +DEF_COND_MINMAX (cond_min, 4, v4sf, <=) +DEF_COND_MINMAX (cond_min, 8, v8sf, <=) +DEF_COND_MINMAX (cond_min, 16, v16sf, <=) +DEF_COND_MINMAX (cond_min, 32, v32sf, <=) +DEF_COND_MINMAX (cond_min, 64, v64sf, <=) +DEF_COND_MINMAX (cond_min, 128, v128sf, <=) +DEF_COND_MINMAX (cond_min, 256, v256sf, <=) +DEF_COND_MINMAX (cond_min, 512, v512sf, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024sf, <=) + +DEF_COND_MINMAX (cond_min, 4, v4df, <=) +DEF_COND_MINMAX (cond_min, 8, v8df, <=) +DEF_COND_MINMAX (cond_min, 16, v16df, <=) +DEF_COND_MINMAX (cond_min, 32, v32df, <=) +DEF_COND_MINMAX (cond_min, 64, v64df, <=) +DEF_COND_MINMAX (cond_min, 128, v128df, <=) +DEF_COND_MINMAX (cond_min, 256, v256df, <=) +DEF_COND_MINMAX (cond_min, 512, v512df, <=) + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c new file mode 100644 index 00000000000..060c58bfe5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_rem, 4, v4si, %) +DEF_COND_BINOP (cond_rem, 8, v8si, %) +DEF_COND_BINOP (cond_rem, 16, v16si, %) +DEF_COND_BINOP (cond_rem, 32, v32si, %) +DEF_COND_BINOP (cond_rem, 64, v64si, %) +DEF_COND_BINOP (cond_rem, 128, v128si, %) +DEF_COND_BINOP (cond_rem, 256, v256si, %) +DEF_COND_BINOP (cond_rem, 512, v512si, %) +DEF_COND_BINOP (cond_rem, 1024, v1024si, %) + +DEF_COND_BINOP (cond_rem, 4, v4di, %) +DEF_COND_BINOP (cond_rem, 8, v8di, %) +DEF_COND_BINOP (cond_rem, 16, v16di, %) +DEF_COND_BINOP (cond_rem, 32, v32di, %) +DEF_COND_BINOP (cond_rem, 64, v64di, %) +DEF_COND_BINOP (cond_rem, 128, v128di, %) +DEF_COND_BINOP (cond_rem, 256, v256di, %) +DEF_COND_BINOP (cond_rem, 512, v512di, %) + +DEF_COND_BINOP (cond_rem, 4, v4usi, %) +DEF_COND_BINOP (cond_rem, 8, v8usi, %) +DEF_COND_BINOP (cond_rem, 16, v16usi, %) +DEF_COND_BINOP (cond_rem, 32, v32usi, %) +DEF_COND_BINOP (cond_rem, 64, v64usi, %) +DEF_COND_BINOP (cond_rem, 128, v128usi, %) +DEF_COND_BINOP (cond_rem, 256, v256usi, %) +DEF_COND_BINOP (cond_rem, 512, v512usi, %) +DEF_COND_BINOP (cond_rem, 1024, v1024usi, %) + +DEF_COND_BINOP (cond_rem, 4, v4udi, %) +DEF_COND_BINOP (cond_rem, 8, v8udi, %) +DEF_COND_BINOP (cond_rem, 16, v16udi, %) +DEF_COND_BINOP (cond_rem, 32, v32udi, %) +DEF_COND_BINOP (cond_rem, 64, v64udi, %) +DEF_COND_BINOP (cond_rem, 128, v128udi, %) +DEF_COND_BINOP (cond_rem, 256, v256udi, %) +DEF_COND_BINOP (cond_rem, 512, v512udi, %) + +/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 34 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c new file mode 100644 index 00000000000..f6b58c101ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_mul, 4, v4qi, *) +DEF_COND_BINOP (cond_mul, 8, v8qi, *) +DEF_COND_BINOP (cond_mul, 16, v16qi, *) +DEF_COND_BINOP (cond_mul, 32, v32qi, *) +DEF_COND_BINOP (cond_mul, 64, v64qi, *) +DEF_COND_BINOP (cond_mul, 128, v128qi, *) +DEF_COND_BINOP (cond_mul, 256, v256qi, *) +DEF_COND_BINOP (cond_mul, 512, v512qi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024qi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048qi, *) +DEF_COND_BINOP (cond_mul, 4096, v4096qi, *) + +DEF_COND_BINOP (cond_mul, 4, v4hi, *) +DEF_COND_BINOP (cond_mul, 8, v8hi, *) +DEF_COND_BINOP (cond_mul, 16, v16hi, *) +DEF_COND_BINOP (cond_mul, 32, v32hi, *) +DEF_COND_BINOP (cond_mul, 64, v64hi, *) +DEF_COND_BINOP (cond_mul, 128, v128hi, *) +DEF_COND_BINOP (cond_mul, 256, v256hi, *) +DEF_COND_BINOP (cond_mul, 512, v512hi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024hi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048hi, *) + +DEF_COND_BINOP (cond_mul, 4, v4si, *) +DEF_COND_BINOP (cond_mul, 8, v8si, *) +DEF_COND_BINOP (cond_mul, 16, v16si, *) +DEF_COND_BINOP (cond_mul, 32, v32si, *) +DEF_COND_BINOP (cond_mul, 64, v64si, *) +DEF_COND_BINOP (cond_mul, 128, v128si, *) +DEF_COND_BINOP (cond_mul, 256, v256si, *) +DEF_COND_BINOP (cond_mul, 512, v512si, *) +DEF_COND_BINOP (cond_mul, 1024, v1024si, *) + +DEF_COND_BINOP (cond_mul, 4, v4di, *) +DEF_COND_BINOP (cond_mul, 8, v8di, *) +DEF_COND_BINOP (cond_mul, 16, v16di, *) +DEF_COND_BINOP (cond_mul, 32, v32di, *) +DEF_COND_BINOP (cond_mul, 64, v64di, *) +DEF_COND_BINOP (cond_mul, 128, v128di, *) +DEF_COND_BINOP (cond_mul, 256, v256di, *) +DEF_COND_BINOP (cond_mul, 512, v512di, *) + +DEF_COND_BINOP (cond_mul, 4, v4uqi, *) +DEF_COND_BINOP (cond_mul, 8, v8uqi, *) +DEF_COND_BINOP (cond_mul, 16, v16uqi, *) +DEF_COND_BINOP (cond_mul, 32, v32uqi, *) +DEF_COND_BINOP (cond_mul, 64, v64uqi, *) +DEF_COND_BINOP (cond_mul, 128, v128uqi, *) +DEF_COND_BINOP (cond_mul, 256, v256uqi, *) +DEF_COND_BINOP (cond_mul, 512, v512uqi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024uqi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048uqi, *) +DEF_COND_BINOP (cond_mul, 4096, v4096uqi, *) + +DEF_COND_BINOP (cond_mul, 4, v4uhi, *) +DEF_COND_BINOP (cond_mul, 8, v8uhi, *) +DEF_COND_BINOP (cond_mul, 16, v16uhi, *) +DEF_COND_BINOP (cond_mul, 32, v32uhi, *) +DEF_COND_BINOP (cond_mul, 64, v64uhi, *) +DEF_COND_BINOP (cond_mul, 128, v128uhi, *) +DEF_COND_BINOP (cond_mul, 256, v256uhi, *) +DEF_COND_BINOP (cond_mul, 512, v512uhi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024uhi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048uhi, *) + +DEF_COND_BINOP (cond_mul, 4, v4usi, *) +DEF_COND_BINOP (cond_mul, 8, v8usi, *) +DEF_COND_BINOP (cond_mul, 16, v16usi, *) +DEF_COND_BINOP (cond_mul, 32, v32usi, *) +DEF_COND_BINOP (cond_mul, 64, v64usi, *) +DEF_COND_BINOP (cond_mul, 128, v128usi, *) +DEF_COND_BINOP (cond_mul, 256, v256usi, *) +DEF_COND_BINOP (cond_mul, 512, v512usi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024usi, *) + +DEF_COND_BINOP (cond_mul, 4, v4udi, *) +DEF_COND_BINOP (cond_mul, 8, v8udi, *) +DEF_COND_BINOP (cond_mul, 16, v16udi, *) +DEF_COND_BINOP (cond_mul, 32, v32udi, *) +DEF_COND_BINOP (cond_mul, 64, v64udi, *) +DEF_COND_BINOP (cond_mul, 128, v128udi, *) +DEF_COND_BINOP (cond_mul, 256, v256udi, *) +DEF_COND_BINOP (cond_mul, 512, v512udi, *) + +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c new file mode 100644 index 00000000000..4df3d5579b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_mul, 4, v4hf, *) +DEF_COND_BINOP (cond_mul, 8, v8hf, *) +DEF_COND_BINOP (cond_mul, 16, v16hf, *) +DEF_COND_BINOP (cond_mul, 32, v32hf, *) +DEF_COND_BINOP (cond_mul, 64, v64hf, *) +DEF_COND_BINOP (cond_mul, 128, v128hf, *) +DEF_COND_BINOP (cond_mul, 256, v256hf, *) +DEF_COND_BINOP (cond_mul, 512, v512hf, *) +DEF_COND_BINOP (cond_mul, 1024, v1024hf, *) +DEF_COND_BINOP (cond_mul, 2048, v2048hf, *) + +DEF_COND_BINOP (cond_mul, 4, v4sf, *) +DEF_COND_BINOP (cond_mul, 8, v8sf, *) +DEF_COND_BINOP (cond_mul, 16, v16sf, *) +DEF_COND_BINOP (cond_mul, 32, v32sf, *) +DEF_COND_BINOP (cond_mul, 64, v64sf, *) +DEF_COND_BINOP (cond_mul, 128, v128sf, *) +DEF_COND_BINOP (cond_mul, 256, v256sf, *) +DEF_COND_BINOP (cond_mul, 512, v512sf, *) +DEF_COND_BINOP (cond_mul, 1024, v1024sf, *) + +DEF_COND_BINOP (cond_mul, 4, v4df, *) +DEF_COND_BINOP (cond_mul, 8, v8df, *) +DEF_COND_BINOP (cond_mul, 16, v16df, *) +DEF_COND_BINOP (cond_mul, 32, v32df, *) +DEF_COND_BINOP (cond_mul, 64, v64df, *) +DEF_COND_BINOP (cond_mul, 128, v128df, *) +DEF_COND_BINOP (cond_mul, 256, v256df, *) +DEF_COND_BINOP (cond_mul, 512, v512df, *) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c new file mode 100644 index 00000000000..ca944460ca7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_neg, 4, v4qi, -) +DEF_COND_UNOP (cond_neg, 8, v8qi, -) +DEF_COND_UNOP (cond_neg, 16, v16qi, -) +DEF_COND_UNOP (cond_neg, 32, v32qi, -) +DEF_COND_UNOP (cond_neg, 64, v64qi, -) +DEF_COND_UNOP (cond_neg, 128, v128qi, -) +DEF_COND_UNOP (cond_neg, 256, v256qi, -) +DEF_COND_UNOP (cond_neg, 512, v512qi, -) +DEF_COND_UNOP (cond_neg, 1024, v1024qi, -) +DEF_COND_UNOP (cond_neg, 2048, v2048qi, -) +DEF_COND_UNOP (cond_neg, 4096, v4096qi, -) + +DEF_COND_UNOP (cond_neg, 4, v4hi, -) +DEF_COND_UNOP (cond_neg, 8, v8hi, -) +DEF_COND_UNOP (cond_neg, 16, v16hi, -) +DEF_COND_UNOP (cond_neg, 32, v32hi, -) +DEF_COND_UNOP (cond_neg, 64, v64hi, -) +DEF_COND_UNOP (cond_neg, 128, v128hi, -) +DEF_COND_UNOP (cond_neg, 256, v256hi, -) +DEF_COND_UNOP (cond_neg, 512, v512hi, -) +DEF_COND_UNOP (cond_neg, 1024, v1024hi, -) +DEF_COND_UNOP (cond_neg, 2048, v2048hi, -) + +DEF_COND_UNOP (cond_neg, 4, v4si, -) +DEF_COND_UNOP (cond_neg, 8, v8si, -) +DEF_COND_UNOP (cond_neg, 16, v16si, -) +DEF_COND_UNOP (cond_neg, 32, v32si, -) +DEF_COND_UNOP (cond_neg, 64, v64si, -) +DEF_COND_UNOP (cond_neg, 128, v128si, -) +DEF_COND_UNOP (cond_neg, 256, v256si, -) +DEF_COND_UNOP (cond_neg, 512, v512si, -) +DEF_COND_UNOP (cond_neg, 1024, v1024si, -) + +DEF_COND_UNOP (cond_neg, 4, v4di, -) +DEF_COND_UNOP (cond_neg, 8, v8di, -) +DEF_COND_UNOP (cond_neg, 16, v16di, -) +DEF_COND_UNOP (cond_neg, 32, v32di, -) +DEF_COND_UNOP (cond_neg, 64, v64di, -) +DEF_COND_UNOP (cond_neg, 128, v128di, -) +DEF_COND_UNOP (cond_neg, 256, v256di, -) +DEF_COND_UNOP (cond_neg, 512, v512di, -) + +/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c new file mode 100644 index 00000000000..cf44c1805e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_neg, 4, v4hf, -) +DEF_COND_UNOP (cond_neg, 8, v8hf, -) +DEF_COND_UNOP (cond_neg, 16, v16hf, -) +DEF_COND_UNOP (cond_neg, 32, v32hf, -) +DEF_COND_UNOP (cond_neg, 64, v64hf, -) +DEF_COND_UNOP (cond_neg, 128, v128hf, -) +DEF_COND_UNOP (cond_neg, 256, v256hf, -) +DEF_COND_UNOP (cond_neg, 512, v512hf, -) +DEF_COND_UNOP (cond_neg, 1024, v1024hf, -) +DEF_COND_UNOP (cond_neg, 2048, v2048hf, -) + +DEF_COND_UNOP (cond_neg, 4, v4sf, -) +DEF_COND_UNOP (cond_neg, 8, v8sf, -) +DEF_COND_UNOP (cond_neg, 16, v16sf, -) +DEF_COND_UNOP (cond_neg, 32, v32sf, -) +DEF_COND_UNOP (cond_neg, 64, v64sf, -) +DEF_COND_UNOP (cond_neg, 128, v128sf, -) +DEF_COND_UNOP (cond_neg, 256, v256sf, -) +DEF_COND_UNOP (cond_neg, 512, v512sf, -) +DEF_COND_UNOP (cond_neg, 1024, v1024sf, -) + +DEF_COND_UNOP (cond_neg, 4, v4df, -) +DEF_COND_UNOP (cond_neg, 8, v8df, -) +DEF_COND_UNOP (cond_neg, 16, v16df, -) +DEF_COND_UNOP (cond_neg, 32, v32df, -) +DEF_COND_UNOP (cond_neg, 64, v64df, -) +DEF_COND_UNOP (cond_neg, 128, v128df, -) +DEF_COND_UNOP (cond_neg, 256, v256df, -) +DEF_COND_UNOP (cond_neg, 512, v512df, -) + +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c new file mode 100644 index 00000000000..1a2a8f45108 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_not, 4, v4qi, ~) +DEF_COND_UNOP (cond_not, 8, v8qi, ~) +DEF_COND_UNOP (cond_not, 16, v16qi, ~) +DEF_COND_UNOP (cond_not, 32, v32qi, ~) +DEF_COND_UNOP (cond_not, 64, v64qi, ~) +DEF_COND_UNOP (cond_not, 128, v128qi, ~) +DEF_COND_UNOP (cond_not, 256, v256qi, ~) +DEF_COND_UNOP (cond_not, 512, v512qi, ~) +DEF_COND_UNOP (cond_not, 1024, v1024qi, ~) +DEF_COND_UNOP (cond_not, 2048, v2048qi, ~) +DEF_COND_UNOP (cond_not, 4096, v4096qi, ~) + +DEF_COND_UNOP (cond_not, 4, v4hi, ~) +DEF_COND_UNOP (cond_not, 8, v8hi, ~) +DEF_COND_UNOP (cond_not, 16, v16hi, ~) +DEF_COND_UNOP (cond_not, 32, v32hi, ~) +DEF_COND_UNOP (cond_not, 64, v64hi, ~) +DEF_COND_UNOP (cond_not, 128, v128hi, ~) +DEF_COND_UNOP (cond_not, 256, v256hi, ~) +DEF_COND_UNOP (cond_not, 512, v512hi, ~) +DEF_COND_UNOP (cond_not, 1024, v1024hi, ~) +DEF_COND_UNOP (cond_not, 2048, v2048hi, ~) + +DEF_COND_UNOP (cond_not, 4, v4si, ~) +DEF_COND_UNOP (cond_not, 8, v8si, ~) +DEF_COND_UNOP (cond_not, 16, v16si, ~) +DEF_COND_UNOP (cond_not, 32, v32si, ~) +DEF_COND_UNOP (cond_not, 64, v64si, ~) +DEF_COND_UNOP (cond_not, 128, v128si, ~) +DEF_COND_UNOP (cond_not, 256, v256si, ~) +DEF_COND_UNOP (cond_not, 512, v512si, ~) +DEF_COND_UNOP (cond_not, 1024, v1024si, ~) + +DEF_COND_UNOP (cond_not, 4, v4di, ~) +DEF_COND_UNOP (cond_not, 8, v8di, ~) +DEF_COND_UNOP (cond_not, 16, v16di, ~) +DEF_COND_UNOP (cond_not, 32, v32di, ~) +DEF_COND_UNOP (cond_not, 64, v64di, ~) +DEF_COND_UNOP (cond_not, 128, v128di, ~) +DEF_COND_UNOP (cond_not, 256, v256di, ~) +DEF_COND_UNOP (cond_not, 512, v512di, ~) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c new file mode 100644 index 00000000000..3ac6203630c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_shift, 4, v4si, >>) +DEF_COND_BINOP (cond_shift, 8, v8si, >>) +DEF_COND_BINOP (cond_shift, 16, v16si, >>) +DEF_COND_BINOP (cond_shift, 32, v32si, >>) +DEF_COND_BINOP (cond_shift, 64, v64si, >>) +DEF_COND_BINOP (cond_shift, 128, v128si, >>) +DEF_COND_BINOP (cond_shift, 256, v256si, >>) +DEF_COND_BINOP (cond_shift, 512, v512si, >>) +DEF_COND_BINOP (cond_shift, 1024, v1024si, >>) + +DEF_COND_BINOP (cond_shift, 4, v4di, >>) +DEF_COND_BINOP (cond_shift, 8, v8di, >>) +DEF_COND_BINOP (cond_shift, 16, v16di, >>) +DEF_COND_BINOP (cond_shift, 32, v32di, >>) +DEF_COND_BINOP (cond_shift, 64, v64di, >>) +DEF_COND_BINOP (cond_shift, 128, v128di, >>) +DEF_COND_BINOP (cond_shift, 256, v256di, >>) + +DEF_COND_BINOP (cond_shift, 4, v4usi, >>) +DEF_COND_BINOP (cond_shift, 8, v8usi, >>) +DEF_COND_BINOP (cond_shift, 16, v16usi, >>) +DEF_COND_BINOP (cond_shift, 32, v32usi, >>) +DEF_COND_BINOP (cond_shift, 64, v64usi, >>) +DEF_COND_BINOP (cond_shift, 128, v128usi, >>) +DEF_COND_BINOP (cond_shift, 256, v256usi, >>) +DEF_COND_BINOP (cond_shift, 512, v512usi, >>) +DEF_COND_BINOP (cond_shift, 1024, v1024usi, >>) + +DEF_COND_BINOP (cond_shift, 4, v4udi, >>) +DEF_COND_BINOP (cond_shift, 8, v8udi, >>) +DEF_COND_BINOP (cond_shift, 16, v16udi, >>) +DEF_COND_BINOP (cond_shift, 32, v32udi, >>) +DEF_COND_BINOP (cond_shift, 64, v64udi, >>) +DEF_COND_BINOP (cond_shift, 128, v128udi, >>) +DEF_COND_BINOP (cond_shift, 256, v256udi, >>) + +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 16 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 16 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c new file mode 100644 index 00000000000..8c2fa470dad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_shift, 4, v4si, <<) +DEF_COND_BINOP (cond_shift, 8, v8si, <<) +DEF_COND_BINOP (cond_shift, 16, v16si, <<) +DEF_COND_BINOP (cond_shift, 32, v32si, <<) +DEF_COND_BINOP (cond_shift, 64, v64si, <<) +DEF_COND_BINOP (cond_shift, 128, v128si, <<) +DEF_COND_BINOP (cond_shift, 256, v256si, <<) +DEF_COND_BINOP (cond_shift, 512, v512si, <<) +DEF_COND_BINOP (cond_shift, 1024, v1024si, <<) + +DEF_COND_BINOP (cond_shift, 4, v4di, <<) +DEF_COND_BINOP (cond_shift, 8, v8di, <<) +DEF_COND_BINOP (cond_shift, 16, v16di, <<) +DEF_COND_BINOP (cond_shift, 32, v32di, <<) +DEF_COND_BINOP (cond_shift, 64, v64di, <<) +DEF_COND_BINOP (cond_shift, 128, v128di, <<) +DEF_COND_BINOP (cond_shift, 256, v256di, <<) + +DEF_COND_BINOP (cond_shift, 4, v4usi, <<) +DEF_COND_BINOP (cond_shift, 8, v8usi, <<) +DEF_COND_BINOP (cond_shift, 16, v16usi, <<) +DEF_COND_BINOP (cond_shift, 32, v32usi, <<) +DEF_COND_BINOP (cond_shift, 64, v64usi, <<) +DEF_COND_BINOP (cond_shift, 128, v128usi, <<) +DEF_COND_BINOP (cond_shift, 256, v256usi, <<) +DEF_COND_BINOP (cond_shift, 512, v512usi, <<) +DEF_COND_BINOP (cond_shift, 1024, v1024usi, <<) + +DEF_COND_BINOP (cond_shift, 4, v4udi, <<) +DEF_COND_BINOP (cond_shift, 8, v8udi, <<) +DEF_COND_BINOP (cond_shift, 16, v16udi, <<) +DEF_COND_BINOP (cond_shift, 32, v32udi, <<) +DEF_COND_BINOP (cond_shift, 64, v64udi, <<) +DEF_COND_BINOP (cond_shift, 128, v128udi, <<) +DEF_COND_BINOP (cond_shift, 256, v256udi, <<) + +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 32 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c new file mode 100644 index 00000000000..629e66cd630 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_sub, 4, v4qi, -) +DEF_COND_BINOP (cond_sub, 8, v8qi, -) +DEF_COND_BINOP (cond_sub, 16, v16qi, -) +DEF_COND_BINOP (cond_sub, 32, v32qi, -) +DEF_COND_BINOP (cond_sub, 64, v64qi, -) +DEF_COND_BINOP (cond_sub, 128, v128qi, -) +DEF_COND_BINOP (cond_sub, 256, v256qi, -) +DEF_COND_BINOP (cond_sub, 512, v512qi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024qi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048qi, -) +DEF_COND_BINOP (cond_sub, 4096, v4096qi, -) + +DEF_COND_BINOP (cond_sub, 4, v4hi, -) +DEF_COND_BINOP (cond_sub, 8, v8hi, -) +DEF_COND_BINOP (cond_sub, 16, v16hi, -) +DEF_COND_BINOP (cond_sub, 32, v32hi, -) +DEF_COND_BINOP (cond_sub, 64, v64hi, -) +DEF_COND_BINOP (cond_sub, 128, v128hi, -) +DEF_COND_BINOP (cond_sub, 256, v256hi, -) +DEF_COND_BINOP (cond_sub, 512, v512hi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024hi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048hi, -) + +DEF_COND_BINOP (cond_sub, 4, v4si, -) +DEF_COND_BINOP (cond_sub, 8, v8si, -) +DEF_COND_BINOP (cond_sub, 16, v16si, -) +DEF_COND_BINOP (cond_sub, 32, v32si, -) +DEF_COND_BINOP (cond_sub, 64, v64si, -) +DEF_COND_BINOP (cond_sub, 128, v128si, -) +DEF_COND_BINOP (cond_sub, 256, v256si, -) +DEF_COND_BINOP (cond_sub, 512, v512si, -) +DEF_COND_BINOP (cond_sub, 1024, v1024si, -) + +DEF_COND_BINOP (cond_sub, 4, v4di, -) +DEF_COND_BINOP (cond_sub, 8, v8di, -) +DEF_COND_BINOP (cond_sub, 16, v16di, -) +DEF_COND_BINOP (cond_sub, 32, v32di, -) +DEF_COND_BINOP (cond_sub, 64, v64di, -) +DEF_COND_BINOP (cond_sub, 128, v128di, -) +DEF_COND_BINOP (cond_sub, 256, v256di, -) +DEF_COND_BINOP (cond_sub, 512, v512di, -) + +DEF_COND_BINOP (cond_sub, 4, v4uqi, -) +DEF_COND_BINOP (cond_sub, 8, v8uqi, -) +DEF_COND_BINOP (cond_sub, 16, v16uqi, -) +DEF_COND_BINOP (cond_sub, 32, v32uqi, -) +DEF_COND_BINOP (cond_sub, 64, v64uqi, -) +DEF_COND_BINOP (cond_sub, 128, v128uqi, -) +DEF_COND_BINOP (cond_sub, 256, v256uqi, -) +DEF_COND_BINOP (cond_sub, 512, v512uqi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024uqi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048uqi, -) +DEF_COND_BINOP (cond_sub, 4096, v4096uqi, -) + +DEF_COND_BINOP (cond_sub, 4, v4uhi, -) +DEF_COND_BINOP (cond_sub, 8, v8uhi, -) +DEF_COND_BINOP (cond_sub, 16, v16uhi, -) +DEF_COND_BINOP (cond_sub, 32, v32uhi, -) +DEF_COND_BINOP (cond_sub, 64, v64uhi, -) +DEF_COND_BINOP (cond_sub, 128, v128uhi, -) +DEF_COND_BINOP (cond_sub, 256, v256uhi, -) +DEF_COND_BINOP (cond_sub, 512, v512uhi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024uhi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048uhi, -) + +DEF_COND_BINOP (cond_sub, 4, v4usi, -) +DEF_COND_BINOP (cond_sub, 8, v8usi, -) +DEF_COND_BINOP (cond_sub, 16, v16usi, -) +DEF_COND_BINOP (cond_sub, 32, v32usi, -) +DEF_COND_BINOP (cond_sub, 64, v64usi, -) +DEF_COND_BINOP (cond_sub, 128, v128usi, -) +DEF_COND_BINOP (cond_sub, 256, v256usi, -) +DEF_COND_BINOP (cond_sub, 512, v512usi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024usi, -) + +DEF_COND_BINOP (cond_sub, 4, v4udi, -) +DEF_COND_BINOP (cond_sub, 8, v8udi, -) +DEF_COND_BINOP (cond_sub, 16, v16udi, -) +DEF_COND_BINOP (cond_sub, 32, v32udi, -) +DEF_COND_BINOP (cond_sub, 64, v64udi, -) +DEF_COND_BINOP (cond_sub, 128, v128udi, -) +DEF_COND_BINOP (cond_sub, 256, v256udi, -) +DEF_COND_BINOP (cond_sub, 512, v512udi, -) + +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c new file mode 100644 index 00000000000..385ab41d173 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_sub, 4, v4hf, -) +DEF_COND_BINOP (cond_sub, 8, v8hf, -) +DEF_COND_BINOP (cond_sub, 16, v16hf, -) +DEF_COND_BINOP (cond_sub, 32, v32hf, -) +DEF_COND_BINOP (cond_sub, 64, v64hf, -) +DEF_COND_BINOP (cond_sub, 128, v128hf, -) +DEF_COND_BINOP (cond_sub, 256, v256hf, -) +DEF_COND_BINOP (cond_sub, 512, v512hf, -) +DEF_COND_BINOP (cond_sub, 1024, v1024hf, -) +DEF_COND_BINOP (cond_sub, 2048, v2048hf, -) + +DEF_COND_BINOP (cond_sub, 4, v4sf, -) +DEF_COND_BINOP (cond_sub, 8, v8sf, -) +DEF_COND_BINOP (cond_sub, 16, v16sf, -) +DEF_COND_BINOP (cond_sub, 32, v32sf, -) +DEF_COND_BINOP (cond_sub, 64, v64sf, -) +DEF_COND_BINOP (cond_sub, 128, v128sf, -) +DEF_COND_BINOP (cond_sub, 256, v256sf, -) +DEF_COND_BINOP (cond_sub, 512, v512sf, -) +DEF_COND_BINOP (cond_sub, 1024, v1024sf, -) + +DEF_COND_BINOP (cond_sub, 4, v4df, -) +DEF_COND_BINOP (cond_sub, 8, v8df, -) +DEF_COND_BINOP (cond_sub, 16, v16df, -) +DEF_COND_BINOP (cond_sub, 32, v32df, -) +DEF_COND_BINOP (cond_sub, 64, v64df, -) +DEF_COND_BINOP (cond_sub, 128, v128df, -) +DEF_COND_BINOP (cond_sub, 256, v256df, -) +DEF_COND_BINOP (cond_sub, 512, v512df, -) + +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c new file mode 100644 index 00000000000..1bb05701773 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_xor, 4, v4qi, ^) +DEF_COND_BINOP (cond_xor, 8, v8qi, ^) +DEF_COND_BINOP (cond_xor, 16, v16qi, ^) +DEF_COND_BINOP (cond_xor, 32, v32qi, ^) +DEF_COND_BINOP (cond_xor, 64, v64qi, ^) +DEF_COND_BINOP (cond_xor, 128, v128qi, ^) +DEF_COND_BINOP (cond_xor, 256, v256qi, ^) +DEF_COND_BINOP (cond_xor, 512, v512qi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024qi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048qi, ^) +DEF_COND_BINOP (cond_xor, 4096, v4096qi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4hi, ^) +DEF_COND_BINOP (cond_xor, 8, v8hi, ^) +DEF_COND_BINOP (cond_xor, 16, v16hi, ^) +DEF_COND_BINOP (cond_xor, 32, v32hi, ^) +DEF_COND_BINOP (cond_xor, 64, v64hi, ^) +DEF_COND_BINOP (cond_xor, 128, v128hi, ^) +DEF_COND_BINOP (cond_xor, 256, v256hi, ^) +DEF_COND_BINOP (cond_xor, 512, v512hi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024hi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048hi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4si, ^) +DEF_COND_BINOP (cond_xor, 8, v8si, ^) +DEF_COND_BINOP (cond_xor, 16, v16si, ^) +DEF_COND_BINOP (cond_xor, 32, v32si, ^) +DEF_COND_BINOP (cond_xor, 64, v64si, ^) +DEF_COND_BINOP (cond_xor, 128, v128si, ^) +DEF_COND_BINOP (cond_xor, 256, v256si, ^) +DEF_COND_BINOP (cond_xor, 512, v512si, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024si, ^) + +DEF_COND_BINOP (cond_xor, 4, v4di, ^) +DEF_COND_BINOP (cond_xor, 8, v8di, ^) +DEF_COND_BINOP (cond_xor, 16, v16di, ^) +DEF_COND_BINOP (cond_xor, 32, v32di, ^) +DEF_COND_BINOP (cond_xor, 64, v64di, ^) +DEF_COND_BINOP (cond_xor, 128, v128di, ^) +DEF_COND_BINOP (cond_xor, 256, v256di, ^) +DEF_COND_BINOP (cond_xor, 512, v512di, ^) + +DEF_COND_BINOP (cond_xor, 4, v4uqi, ^) +DEF_COND_BINOP (cond_xor, 8, v8uqi, ^) +DEF_COND_BINOP (cond_xor, 16, v16uqi, ^) +DEF_COND_BINOP (cond_xor, 32, v32uqi, ^) +DEF_COND_BINOP (cond_xor, 64, v64uqi, ^) +DEF_COND_BINOP (cond_xor, 128, v128uqi, ^) +DEF_COND_BINOP (cond_xor, 256, v256uqi, ^) +DEF_COND_BINOP (cond_xor, 512, v512uqi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024uqi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048uqi, ^) +DEF_COND_BINOP (cond_xor, 4096, v4096uqi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4uhi, ^) +DEF_COND_BINOP (cond_xor, 8, v8uhi, ^) +DEF_COND_BINOP (cond_xor, 16, v16uhi, ^) +DEF_COND_BINOP (cond_xor, 32, v32uhi, ^) +DEF_COND_BINOP (cond_xor, 64, v64uhi, ^) +DEF_COND_BINOP (cond_xor, 128, v128uhi, ^) +DEF_COND_BINOP (cond_xor, 256, v256uhi, ^) +DEF_COND_BINOP (cond_xor, 512, v512uhi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024uhi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048uhi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4usi, ^) +DEF_COND_BINOP (cond_xor, 8, v8usi, ^) +DEF_COND_BINOP (cond_xor, 16, v16usi, ^) +DEF_COND_BINOP (cond_xor, 32, v32usi, ^) +DEF_COND_BINOP (cond_xor, 64, v64usi, ^) +DEF_COND_BINOP (cond_xor, 128, v128usi, ^) +DEF_COND_BINOP (cond_xor, 256, v256usi, ^) +DEF_COND_BINOP (cond_xor, 512, v512usi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024usi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4udi, ^) +DEF_COND_BINOP (cond_xor, 8, v8udi, ^) +DEF_COND_BINOP (cond_xor, 16, v16udi, ^) +DEF_COND_BINOP (cond_xor, 32, v32udi, ^) +DEF_COND_BINOP (cond_xor, 64, v64udi, ^) +DEF_COND_BINOP (cond_xor, 128, v128udi, ^) +DEF_COND_BINOP (cond_xor, 256, v256udi, ^) +DEF_COND_BINOP (cond_xor, 512, v512udi, ^) + +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 26671b2975c..39495efe025 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -526,3 +526,73 @@ typedef double v512df __attribute__ ((vector_size (4096))); for (int i = 0; i < NUM; ++i) \ dst[i] = src[i] % 19; \ } + +#define DEF_COND_UNOP(PREFIX, NUM, TYPE, OP) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? OP (a[i]) : b[i]; \ + return v; \ + } + +#define DEF_COND_BINOP(PREFIX, NUM, TYPE, OP) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] OP b[i] : c[i]; \ + return v; \ + } + +#define DEF_COND_MINMAX(PREFIX, NUM, TYPE, OP) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? ((a[i]) OP (b[i]) ? (a[i]) : (b[i])) : c[i]; \ + return v; \ + } + +#define DEF_COND_FMA_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] * b[i] + c[i] : b[i]; \ + return v; \ + } + +#define DEF_COND_FNMA_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] - b[i] * c[i] : b[i]; \ + return v; \ + } + +#define DEF_COND_FMS_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] * b[i] - c[i] : b[i]; \ + return v; \ + } + +#define DEF_COND_FNMS_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? -(a[i] * b[i]) - c[i] : b[i]; \ + return v; \ + }