RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
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Commit Message
From: xuli <xuli1@eswincomputing.com>
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{ \
TYPE v \
= __builtin_shufflevector (values1, values2, MASK_##NUNITS (0, NUNITS)); \
*(TYPE *) out = v; \
}
T (vnx32si, 32) \
TEST_ALL (PERMUTE)
Before this patch:
li a4,31
vsetvli a5,zero,e32,m8,ta,ma
vl8re32.v v24,0(a0)
vid.v v8
vrsub.vx v8,v8,a4
vrgather.vv v16,v24,v8
vs8r.v v16,0(a2)
ret
The index vector register "v8" occupies 8 registers.
We should optimize it into vrgatherei16.vv which is
using int16 as the index elements.
After this patch:
vsetvli a5,zero,e16,m4,ta,ma
li a4,31
vid.v v4
vl8re32.v v16,0(a0)
vrsub.vx v4,v4,a4
vsetvli zero,zero,e32,m8,ta,ma
vrgatherei16.vv v8,v16,v4
vs8r.v v8,0(a2)
ret
With vrgatherei16.vv, the v8 will occupy 4 registers instead
of 8. Lower the register consuming and register pressure.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of vrgather.vv into vrgatherei16.vv.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case.
* gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto.
---
gcc/config/riscv/riscv-v.cc | 20 +++++++++++++++++++
.../riscv/rvv/autovec/vls-vlmax/perm-4.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 3 ++-
3 files changed, 24 insertions(+), 2 deletions(-)
Comments
+ unsigned int data_sew = get_sew (data_mode);
+ enum vlmul_type data_lmul = get_vlmul (data_mode);
Remove this.
+ else if (CONST_VECTOR_P (sel) && data_sew != 16
+ && data_sew != 8 && (data_lmul == LMUL_2
+ || data_lmul == LMUL_4 || data_lmul == LMUL_8))
change it into:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > LMUL_1)
juzhe.zhong@rivai.ai
From: Li Xu
Date: 2023-09-22 09:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
From: xuli <xuli1@eswincomputing.com>
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{ \
TYPE v \
= __builtin_shufflevector (values1, values2, MASK_##NUNITS (0, NUNITS)); \
*(TYPE *) out = v; \
}
T (vnx32si, 32) \
TEST_ALL (PERMUTE)
Before this patch:
li a4,31
vsetvli a5,zero,e32,m8,ta,ma
vl8re32.v v24,0(a0)
vid.v v8
vrsub.vx v8,v8,a4
vrgather.vv v16,v24,v8
vs8r.v v16,0(a2)
ret
The index vector register "v8" occupies 8 registers.
We should optimize it into vrgatherei16.vv which is
using int16 as the index elements.
After this patch:
vsetvli a5,zero,e16,m4,ta,ma
li a4,31
vid.v v4
vl8re32.v v16,0(a0)
vrsub.vx v4,v4,a4
vsetvli zero,zero,e32,m8,ta,ma
vrgatherei16.vv v8,v16,v4
vs8r.v v8,0(a2)
ret
With vrgatherei16.vv, the v8 will occupy 4 registers instead
of 8. Lower the register consuming and register pressure.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of vrgather.vv into vrgatherei16.vv.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case.
* gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto.
---
gcc/config/riscv/riscv-v.cc | 20 +++++++++++++++++++
.../riscv/rvv/autovec/vls-vlmax/perm-4.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 3 ++-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 64a71a128d4..271e0ff6dfc 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -783,6 +783,8 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
insn_code icode;
machine_mode data_mode = GET_MODE (target);
machine_mode sel_mode = GET_MODE (sel);
+ unsigned int data_sew = get_sew (data_mode);
+ enum vlmul_type data_lmul = get_vlmul (data_mode);
if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode)))
icode = code_for_pred_gatherei16 (data_mode);
else if (const_vec_duplicate_p (sel, &elt))
@@ -790,6 +792,24 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
icode = code_for_pred_gather_scalar (data_mode);
sel = elt;
}
+ else if (CONST_VECTOR_P (sel) && data_sew != 16
+ && data_sew != 8 && (data_lmul == LMUL_2
+ || data_lmul == LMUL_4 || data_lmul == LMUL_8))
+ {
+ /* If the inner mode of data is not QI or HI and data_lmul > 1,
+ emitting vrgatherei16.vv instruction will lower register
+ pressure.
+ data_mode sel_mode ei16
+ RVVM1QI RVVM1QI RVVM2HI not needed
+ RVVM2QI RVVM2QI RVVM4HI not needed
+ RVVM2HI RVVM2HI RVVM2HI not needed
+ RVVM2SI RVVM2SI RVVM1HI need
+ RVVM4SI RVVM4SI RVVM2HI need
+ RVVM8DI RVVM8DI RVVM2HI need */
+ PUT_MODE (sel, get_vector_mode (HImode,
+ GET_MODE_NUNITS (data_mode)).require ());
+ icode = code_for_pred_gatherei16 (data_mode);
+ }
else
icode = code_for_pred_gather (data_mode);
rtx ops[] = {target, op, sel};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index 9df69a0cc2c..7ab31043547 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -55,6 +55,7 @@
TEST_ALL (PERMUTE)
-/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
index 46cad8ea2f4..4d6862cf1c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
@@ -3,6 +3,7 @@
#include "../vls-vlmax/perm-4.c"
-/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
--
2.17.1
Sorry. It should be:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > 1)
juzhe.zhong@rivai.ai
From: juzhe.zhong@rivai.ai
Date: 2023-09-22 09:39
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
+ unsigned int data_sew = get_sew (data_mode);
+ enum vlmul_type data_lmul = get_vlmul (data_mode);
Remove this.
+ else if (CONST_VECTOR_P (sel) && data_sew != 16
+ && data_sew != 8 && (data_lmul == LMUL_2
+ || data_lmul == LMUL_4 || data_lmul == LMUL_8))
change it into:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > LMUL_1)
juzhe.zhong@rivai.ai
From: Li Xu
Date: 2023-09-22 09:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
From: xuli <xuli1@eswincomputing.com>
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{ \
TYPE v \
= __builtin_shufflevector (values1, values2, MASK_##NUNITS (0, NUNITS)); \
*(TYPE *) out = v; \
}
T (vnx32si, 32) \
TEST_ALL (PERMUTE)
Before this patch:
li a4,31
vsetvli a5,zero,e32,m8,ta,ma
vl8re32.v v24,0(a0)
vid.v v8
vrsub.vx v8,v8,a4
vrgather.vv v16,v24,v8
vs8r.v v16,0(a2)
ret
The index vector register "v8" occupies 8 registers.
We should optimize it into vrgatherei16.vv which is
using int16 as the index elements.
After this patch:
vsetvli a5,zero,e16,m4,ta,ma
li a4,31
vid.v v4
vl8re32.v v16,0(a0)
vrsub.vx v4,v4,a4
vsetvli zero,zero,e32,m8,ta,ma
vrgatherei16.vv v8,v16,v4
vs8r.v v8,0(a2)
ret
With vrgatherei16.vv, the v8 will occupy 4 registers instead
of 8. Lower the register consuming and register pressure.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of vrgather.vv into vrgatherei16.vv.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case.
* gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto.
---
gcc/config/riscv/riscv-v.cc | 20 +++++++++++++++++++
.../riscv/rvv/autovec/vls-vlmax/perm-4.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 3 ++-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 64a71a128d4..271e0ff6dfc 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -783,6 +783,8 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
insn_code icode;
machine_mode data_mode = GET_MODE (target);
machine_mode sel_mode = GET_MODE (sel);
+ unsigned int data_sew = get_sew (data_mode);
+ enum vlmul_type data_lmul = get_vlmul (data_mode);
if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode)))
icode = code_for_pred_gatherei16 (data_mode);
else if (const_vec_duplicate_p (sel, &elt))
@@ -790,6 +792,24 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
icode = code_for_pred_gather_scalar (data_mode);
sel = elt;
}
+ else if (CONST_VECTOR_P (sel) && data_sew != 16
+ && data_sew != 8 && (data_lmul == LMUL_2
+ || data_lmul == LMUL_4 || data_lmul == LMUL_8))
+ {
+ /* If the inner mode of data is not QI or HI and data_lmul > 1,
+ emitting vrgatherei16.vv instruction will lower register
+ pressure.
+ data_mode sel_mode ei16
+ RVVM1QI RVVM1QI RVVM2HI not needed
+ RVVM2QI RVVM2QI RVVM4HI not needed
+ RVVM2HI RVVM2HI RVVM2HI not needed
+ RVVM2SI RVVM2SI RVVM1HI need
+ RVVM4SI RVVM4SI RVVM2HI need
+ RVVM8DI RVVM8DI RVVM2HI need */
+ PUT_MODE (sel, get_vector_mode (HImode,
+ GET_MODE_NUNITS (data_mode)).require ());
+ icode = code_for_pred_gatherei16 (data_mode);
+ }
else
icode = code_for_pred_gather (data_mode);
rtx ops[] = {target, op, sel};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index 9df69a0cc2c..7ab31043547 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -55,6 +55,7 @@
TEST_ALL (PERMUTE)
-/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
index 46cad8ea2f4..4d6862cf1c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
@@ -3,6 +3,7 @@
#include "../vls-vlmax/perm-4.c"
-/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
--
2.17.1
@@ -783,6 +783,8 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
insn_code icode;
machine_mode data_mode = GET_MODE (target);
machine_mode sel_mode = GET_MODE (sel);
+ unsigned int data_sew = get_sew (data_mode);
+ enum vlmul_type data_lmul = get_vlmul (data_mode);
if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode)))
icode = code_for_pred_gatherei16 (data_mode);
else if (const_vec_duplicate_p (sel, &elt))
@@ -790,6 +792,24 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
icode = code_for_pred_gather_scalar (data_mode);
sel = elt;
}
+ else if (CONST_VECTOR_P (sel) && data_sew != 16
+ && data_sew != 8 && (data_lmul == LMUL_2
+ || data_lmul == LMUL_4 || data_lmul == LMUL_8))
+ {
+ /* If the inner mode of data is not QI or HI and data_lmul > 1,
+ emitting vrgatherei16.vv instruction will lower register
+ pressure.
+ data_mode sel_mode ei16
+ RVVM1QI RVVM1QI RVVM2HI not needed
+ RVVM2QI RVVM2QI RVVM4HI not needed
+ RVVM2HI RVVM2HI RVVM2HI not needed
+ RVVM2SI RVVM2SI RVVM1HI need
+ RVVM4SI RVVM4SI RVVM2HI need
+ RVVM8DI RVVM8DI RVVM2HI need */
+ PUT_MODE (sel, get_vector_mode (HImode,
+ GET_MODE_NUNITS (data_mode)).require ());
+ icode = code_for_pred_gatherei16 (data_mode);
+ }
else
icode = code_for_pred_gather (data_mode);
rtx ops[] = {target, op, sel};
@@ -55,6 +55,7 @@
TEST_ALL (PERMUTE)
-/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
@@ -3,6 +3,7 @@
#include "../vls-vlmax/perm-4.c"
-/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */