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[8.43.85.97]) by mx.google.com with ESMTPS id k4-20020aa7c384000000b0053323e20c43si965975edq.146.2023.09.21.04.54.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 04:54:48 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BCA023858C2B for ; Thu, 21 Sep 2023 11:54:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 2A1103858C27 for ; Thu, 21 Sep 2023 11:54:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2A1103858C27 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp83t1695297252tiwid1yd Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 21 Sep 2023 19:54:11 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBfkYtYigxC4da9cOus25C03ZwuLYsK9vPSFyxGu7wm5UA9CV0/puU jw1/gqmUlsD6q4fakvwvnlx4+4Z0URNvWUhMDJFDXw5pdGT6rChOzlBfB38+2LtXkwcuzO5 Rb7BpqlCoXpvA5uRatlwlMyCKHbTT+H2cwkDgO9CgoUDj2tI3HWC9rEyxKLOQF2dkUTwb4P NDwp7U6G1vwJ+sWvy0hPH375YWDiuFdz/1BCTcm2HjFcx2mL3iKvqn22QievCnXF7D93s41 YSctWEqxWLE2t59vot/8AOFAWUGhwtExdGNYcQHq9MiQC8pqYSDnyoQjfU9voWcuVOw86cc PNmKckZWIUJ89qjSQEC6hiZp7isgARxmell8IpDX7BKO89sQxt/r3cCJzJXS2P39IgixEuu L5JVRDx6caRCXPnxlb9nqQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 7114976247807276983 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [Committed] RISC-V: Support VLS mult high Date: Thu, 21 Sep 2023 19:54:10 +0800 Message-Id: <20230921115410.1393445-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777648049601830954 X-GMAIL-MSGID: 1777648049601830954 Regression passed. Committed. gcc/ChangeLog: * config/riscv/vector-iterators.md: Extend VLS modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mult high. * gcc.target/riscv/rvv/autovec/vls/mulh-1.c: New test. --- gcc/config/riscv/vector-iterators.md | 47 ++++++++ .../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++ .../gcc.target/riscv/rvv/autovec/vls/mulh-1.c | 104 ++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 5c4b433c6bf..4aa64127df7 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -670,6 +670,53 @@ RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V") (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V") + + (V1QI "TARGET_VECTOR_VLS") + (V2QI "TARGET_VECTOR_VLS") + (V4QI "TARGET_VECTOR_VLS") + (V8QI "TARGET_VECTOR_VLS") + (V16QI "TARGET_VECTOR_VLS") + (V32QI "TARGET_VECTOR_VLS") + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1HI "TARGET_VECTOR_VLS") + (V2HI "TARGET_VECTOR_VLS") + (V4HI "TARGET_VECTOR_VLS") + (V8HI "TARGET_VECTOR_VLS") + (V16HI "TARGET_VECTOR_VLS") + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1SI "TARGET_VECTOR_VLS") + (V2SI "TARGET_VECTOR_VLS") + (V4SI "TARGET_VECTOR_VLS") + (V8SI "TARGET_VECTOR_VLS") + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1DI "TARGET_VECTOR_VLS && TARGET_FULL_V") + (V2DI "TARGET_VECTOR_VLS && TARGET_FULL_V") + (V4DI "TARGET_VECTOR_VLS && TARGET_FULL_V") + (V8DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 64") + (V16DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 128") + (V32DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 256") + (V64DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 512") + (V128DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 1024") + (V256DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 2048") + (V512DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 4096") ]) (define_mode_iterator VI_QH [ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 74685f8d05e..26671b2975c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -518,3 +518,11 @@ typedef double v512df __attribute__ ((vector_size (4096))); for (int i = 0; i < NUM; i++) \ dst[i] = ((TYPE2) a[i] + b[i] + 1) >> 1; \ } + +#define DEF_MULH(TYPE, NUM) \ + void __attribute__ ((noipa)) \ + mod_##TYPE##_##NUM (TYPE *__restrict dst, TYPE *__restrict src) \ + { \ + for (int i = 0; i < NUM; ++i) \ + dst[i] = src[i] % 19; \ + } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c new file mode 100644 index 00000000000..47bb40f9828 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_MULH (int8_t, 4) +DEF_MULH (int8_t, 8) +DEF_MULH (int8_t, 16) +DEF_MULH (int8_t, 32) +DEF_MULH (int8_t, 64) +DEF_MULH (int8_t, 128) +DEF_MULH (int8_t, 256) +DEF_MULH (int8_t, 512) +DEF_MULH (int8_t, 1024) +DEF_MULH (int8_t, 2048) +DEF_MULH (int8_t, 4096) + +DEF_MULH (int16_t, 4) +DEF_MULH (int16_t, 8) +DEF_MULH (int16_t, 16) +DEF_MULH (int16_t, 32) +DEF_MULH (int16_t, 64) +DEF_MULH (int16_t, 128) +DEF_MULH (int16_t, 256) +DEF_MULH (int16_t, 512) +DEF_MULH (int16_t, 1024) +DEF_MULH (int16_t, 2048) + +DEF_MULH (int32_t, 4) +DEF_MULH (int32_t, 8) +DEF_MULH (int32_t, 16) +DEF_MULH (int32_t, 32) +DEF_MULH (int32_t, 64) +DEF_MULH (int32_t, 128) +DEF_MULH (int32_t, 256) +DEF_MULH (int32_t, 512) +DEF_MULH (int32_t, 1024) + +DEF_MULH (int64_t, 4) +DEF_MULH (int64_t, 8) +DEF_MULH (int64_t, 16) +DEF_MULH (int64_t, 32) +DEF_MULH (int64_t, 64) +DEF_MULH (int64_t, 128) +DEF_MULH (int64_t, 256) +DEF_MULH (int64_t, 512) + +DEF_MULH (uint8_t, 4) +DEF_MULH (uint8_t, 8) +DEF_MULH (uint8_t, 16) +DEF_MULH (uint8_t, 32) +DEF_MULH (uint8_t, 64) +DEF_MULH (uint8_t, 128) +DEF_MULH (uint8_t, 256) +DEF_MULH (uint8_t, 512) +DEF_MULH (uint8_t, 1024) +DEF_MULH (uint8_t, 2048) +DEF_MULH (uint8_t, 4096) + +DEF_MULH (uint16_t, 4) +DEF_MULH (uint16_t, 8) +DEF_MULH (uint16_t, 16) +DEF_MULH (uint16_t, 32) +DEF_MULH (uint16_t, 64) +DEF_MULH (uint16_t, 128) +DEF_MULH (uint16_t, 256) +DEF_MULH (uint16_t, 512) +DEF_MULH (uint16_t, 1024) +DEF_MULH (uint16_t, 2048) + +DEF_MULH (uint32_t, 4) +DEF_MULH (uint32_t, 8) +DEF_MULH (uint32_t, 16) +DEF_MULH (uint32_t, 32) +DEF_MULH (uint32_t, 64) +DEF_MULH (uint32_t, 128) +DEF_MULH (uint32_t, 256) +DEF_MULH (uint32_t, 512) +DEF_MULH (uint32_t, 1024) + +DEF_MULH (uint64_t, 4) +DEF_MULH (uint64_t, 8) +DEF_MULH (uint64_t, 16) +DEF_MULH (uint64_t, 32) +DEF_MULH (uint64_t, 64) +DEF_MULH (uint64_t, 128) +DEF_MULH (uint64_t, 256) +DEF_MULH (uint64_t, 512) + +/* { dg-final { scan-assembler-times {vmulh\.} 38 } } */ +/* { dg-final { scan-assembler-times {vmulhu\.} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */