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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d7-20020a170906370700b009ae027abbc0si709923ejc.1034.2023.09.21.00.26.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 00:26:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Jbp60+fV; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EA0B93882039 for ; Thu, 21 Sep 2023 07:23:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 24F493858418 for ; Thu, 21 Sep 2023 07:22:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 24F493858418 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695280956; x=1726816956; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XuMxU+Grrtp2C3ozqnJycAT1vncS8fqkijJNTgd9POE=; b=Jbp60+fVBIexQX9JTPIbwwf1qakhrUg3g3DOI0Q7E8TZPD559oTjMOZh aquOahSxWdQYxbdUzC5A/2m9Dzf1pRrp2J72l0B96x+7PD7W4874ICU+C NSieidjHDn1mbnd2KRx2KOzS1bmNJIA1ihMc1c2nMUg/j5UL7IrqHdop9 ZtVNs60tWAO76Twvi7QW9ia7hDOtG2PPrmAMu7Pl5wmsR7q3b0v4sNhhD aLp5Ij4W1oOrfKAoTXxXA2U7IoSyTm4kW2QFVPLN4nLgn07qA6M4Sz8cs NgEdG5+8e+R1s9GkXhnQJVPoVN/gTb1QO9Jdjo2Dl4Fyh1xCKO1L0QbSC A==; X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="380352146" X-IronPort-AV: E=Sophos;i="6.03,164,1694761200"; d="scan'208";a="380352146" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2023 00:22:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="817262181" X-IronPort-AV: E=Sophos;i="6.03,164,1694761200"; d="scan'208";a="817262181" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 21 Sep 2023 00:22:15 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5FD8E100513C; Thu, 21 Sep 2023 15:22:14 +0800 (CST) From: "Hu, Lin1" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, haochen.jiang@intel.com Subject: [PATCH 14/18] Support -mevex512 for AVX512DQ intrins Date: Thu, 21 Sep 2023 15:20:09 +0800 Message-Id: <20230921072013.2124750-15-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230921072013.2124750-1-lin1.hu@intel.com> References: <20230921072013.2124750-1-lin1.hu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777631161650085788 X-GMAIL-MSGID: 1777631161650085788 From: Haochen Jiang gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_sse2_mulvxdi3): Add TARGET_EVEX512 for 512 bit usage. * config/i386/i386.cc (standard_sse_constant_opcode): Ditto. * config/i386/sse.md (VF1_VF2_AVX512DQ): Ditto. (VF1_128_256VL): Ditto. (VF2_AVX512VL): Ditto. (VI8_256_512): Ditto. (fixuns_trunc2): Ditto. (AVX512_VEC): Ditto. (AVX512_VEC_2): Ditto. (VI4F_BRCST32x2): Ditto. (VI8F_BRCST64x2): Ditto. --- gcc/config/i386/i386-expand.cc | 2 +- gcc/config/i386/i386.cc | 22 ++++++++++++++++------ gcc/config/i386/sse.md | 24 ++++++++++++++---------- 3 files changed, 31 insertions(+), 17 deletions(-) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 0705e08d38c..063561e1265 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -24008,7 +24008,7 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2) machine_mode mode = GET_MODE (op0); rtx t1, t2, t3, t4, t5, t6; - if (TARGET_AVX512DQ && mode == V8DImode) + if (TARGET_AVX512DQ && TARGET_EVEX512 && mode == V8DImode) emit_insn (gen_avx512dq_mulv8di3 (op0, op1, op2)); else if (TARGET_AVX512DQ && TARGET_AVX512VL && mode == V4DImode) emit_insn (gen_avx512dq_mulv4di3 (op0, op1, op2)); diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 635dd85e764..589b29a324d 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -5332,9 +5332,14 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) if (EXT_REX_SSE_REG_P (operands[0])) { if (TARGET_AVX512DQ) - return (TARGET_AVX512VL - ? "vxorpd\t%x0, %x0, %x0" - : "vxorpd\t%g0, %g0, %g0"); + { + if (TARGET_AVX512VL) + return "vxorpd\t%x0, %x0, %x0"; + else if (TARGET_EVEX512) + return "vxorpd\t%g0, %g0, %g0"; + else + gcc_unreachable (); + } else { if (TARGET_AVX512VL) @@ -5356,9 +5361,14 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) if (EXT_REX_SSE_REG_P (operands[0])) { if (TARGET_AVX512DQ) - return (TARGET_AVX512VL - ? "vxorps\t%x0, %x0, %x0" - : "vxorps\t%g0, %g0, %g0"); + { + if (TARGET_AVX512VL) + return "vxorps\t%x0, %x0, %x0"; + else if (TARGET_EVEX512) + return "vxorps\t%g0, %g0, %g0"; + else + gcc_unreachable (); + } else { if (TARGET_AVX512VL) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8d1b75b43e0..a8f93ceddc5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -350,7 +350,8 @@ (define_mode_iterator VF1_VF2_AVX512DQ [(V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512DQ") (V4DF "TARGET_AVX512DQ && TARGET_AVX512VL") + (V8DF "TARGET_AVX512DQ && TARGET_EVEX512") + (V4DF "TARGET_AVX512DQ && TARGET_AVX512VL") (V2DF "TARGET_AVX512DQ && TARGET_AVX512VL")]) (define_mode_iterator VFH @@ -392,7 +393,7 @@ [(V8SF "TARGET_AVX") V4SF]) (define_mode_iterator VF1_128_256VL - [V8SF (V4SF "TARGET_AVX512VL")]) + [(V8SF "TARGET_EVEX512") (V4SF "TARGET_AVX512VL")]) ;; All DFmode vector float modes (define_mode_iterator VF2 @@ -467,7 +468,7 @@ (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator VF2_AVX512VL - [V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + [(V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator VF1_AVX512VL [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")]) @@ -534,7 +535,7 @@ [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI8_256_512 - [V8DI (V4DI "TARGET_AVX512VL")]) + [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL")]) (define_mode_iterator VI1_AVX2 [(V32QI "TARGET_AVX2") V16QI]) @@ -9075,7 +9076,7 @@ (define_insn "fixuns_trunc2" [(set (match_operand: 0 "register_operand" "=v") (unsigned_fix: - (match_operand:VF1_128_256VL 1 "nonimmediate_operand" "vm")))] + (match_operand:VF1_128_256 1 "nonimmediate_operand" "vm")))] "TARGET_AVX512VL" "vcvttps2udq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") @@ -11466,7 +11467,8 @@ (V8SF "32x4") (V8SI "32x4") (V4DF "64x2") (V4DI "64x2")]) (define_mode_iterator AVX512_VEC - [(V8DF "TARGET_AVX512DQ") (V8DI "TARGET_AVX512DQ") + [(V8DF "TARGET_AVX512DQ && TARGET_EVEX512") + (V8DI "TARGET_AVX512DQ && TARGET_EVEX512") (V16SF "TARGET_EVEX512") (V16SI "TARGET_EVEX512")]) (define_expand "_vextract_mask" @@ -11636,7 +11638,8 @@ [(V16SF "32x8") (V16SI "32x8") (V8DF "64x4") (V8DI "64x4")]) (define_mode_iterator AVX512_VEC_2 - [(V16SF "TARGET_AVX512DQ") (V16SI "TARGET_AVX512DQ") + [(V16SF "TARGET_AVX512DQ && TARGET_EVEX512") + (V16SI "TARGET_AVX512DQ && TARGET_EVEX512") (V8DF "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) (define_expand "_vextract_mask" @@ -26850,8 +26853,8 @@ ;; For broadcast[i|f]32x2. Yes there is no v4sf version, only v4si. (define_mode_iterator VI4F_BRCST32x2 - [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - V16SF (V8SF "TARGET_AVX512VL")]) + [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL")]) (define_mode_attr 64x2mode [(V8DF "V2DF") (V8DI "V2DI") (V4DI "V2DI") (V4DF "V2DF")]) @@ -26901,7 +26904,8 @@ ;; For broadcast[i|f]64x2 (define_mode_iterator VI8F_BRCST64x2 - [V8DI V8DF (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) + [(V8DI "TARGET_EVEX512") (V8DF "TARGET_EVEX512") + (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) (define_insn "avx512dq_broadcast_1" [(set (match_operand:VI8F_BRCST64x2 0 "register_operand" "=v,v")