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[8.43.85.97]) by mx.google.com with ESMTPS id z15-20020a170906944f00b009adec4bd97asi828293ejx.453.2023.09.21.00.12.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 00:12:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D10F9385C6E9 for ; Thu, 21 Sep 2023 07:12:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 236D33858C2B for ; Thu, 21 Sep 2023 07:11:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 236D33858C2B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1695280279twfe54yb Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 21 Sep 2023 15:11:18 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: oAZ4GxcAC/VdFDMHxRafbyly+U+xn7uWfeFo4KMajZPKZE9Omk0RJ9qQhlbWX 4sFXHXHVsaqW2qlcT8uZVGvHsIOaW7RZMOAbFT6o0NtNxhCvWDKcSYebK3tRUiV1hCEh6pb A9G9XbeRm6xTw8mtO7iTVbk8su/MMj1sDi60yKnSkwMvpbUPqRTRPrqtsnrAMxy9biTdS4h RNV0e3rhYGAIoKez4gFFgyQZURA8y97BJmIKr/u8ogpidr5eblHSr+0sOIBNsC8Ef5jJuHR Y8lavsXwNDSjpaiBGqdueglU53izPqV9VZX3RGGaKTDOKDMl1oKH7r+3EWKJGa1JG7MlR3K plJ7PaREPApKepUM8Ma/oEkfelSt5XiyBAKdPx+sWEW/SfgvdDGe/AFE6dwIqFZnIUmOGjC YxVIpeu0kAU= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 731445130059853050 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions Date: Thu, 21 Sep 2023 15:11:18 +0800 Message-Id: <20230921071118.3321383-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777630277972094071 X-GMAIL-MSGID: 1777630277972094071 This patch adjusts the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions. The purpose of the adjustment is to make it clear that vlmax here is not VLMAX as defined inside the RVV ISA. This is because this function is used by RVV mode (e.g. RVVM1SImode) in addition to VLS mode (V16QI). For RVV mode, it means the same thing, for VLS mode, it indicates setting the vl to the number of units of the mode. Changed the comment because I didn't think of a better name. If there is a suitable name, feel free to discuss it. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_nonvlmax_insn): Adjust comments. (emit_vlmax_insn_lra): Adjust comments. --- gcc/config/riscv/riscv-v.cc | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) -- 2.36.3 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 64a71a128d4..df4d2ac1b2b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -347,9 +347,8 @@ private: expand_operand m_ops[MAX_OPERANDS]; }; -/* Emit RVV insn which vl is VLMAX. - This function can only be used before LRA pass or - for VLS_AVL_IMM modes. */ +/* Emit RVV insn which vl is the number of units of the vector mode. + This function can only be used before LRA pass or for VLS_AVL_IMM modes. */ void emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops) { @@ -357,23 +356,23 @@ emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops) e.emit_insn ((enum insn_code) icode, ops); } -/* Emit RVV insn which vl is VL. */ +/* Like emit_vlmax_insn but can be only used after LRA pass that can't create + pseudo register. */ void -emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) +emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { - insn_expander e (insn_flags, false); + gcc_assert (!can_create_pseudo_p ()); + + insn_expander e (insn_flags, true); e.set_vl (vl); e.emit_insn ((enum insn_code) icode, ops); } -/* Emit RVV insn which vl is VL but the AVL_TYPE insn attr is VLMAX. - This function used after LRA pass that cann't create pseudo register. */ +/* Emit RVV insn which vl is the VL argument. */ void -emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) +emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { - gcc_assert (!can_create_pseudo_p ()); - - insn_expander e (insn_flags, true); + insn_expander e (insn_flags, false); e.set_vl (vl); e.emit_insn ((enum insn_code) icode, ops); }