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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id x2-20020aa7d382000000b0052888f9cdbdsi7252145edq.326.2023.09.20.00.04.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 00:04:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4DCD63858D39 for ; Wed, 20 Sep 2023 07:04:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id E45673858D20 for ; Wed, 20 Sep 2023 07:03:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E45673858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp84t1695193392tx8oquxw Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 20 Sep 2023 15:03:11 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: IByDngDI/kGEiRN0stW3cy7mQv2tMiNen721nv+pL25gHqvjCj5dSDj3RAhxu UW+XZdT5j3wCNCXOLj+yrMvUZVt7AHKgqJeSuruMJaDL7SJTHNTO6PjchB9pahJsqBwh2ll xuQ2UCeiYPXskn63+CfMpM5NalXDXH1O0J+CGPpKS20vCh1fG0G41M2sELjzRPI33WNah7q 10z2VP+PGtZ4r/GoLfwvvDymMsuuj9GjEIE70Q34Y5NeneM1l/uTO6wo3miF5XSC4bKKAQk wNX0gUNeJlZsoaQLEGuvFcTI/aVPQy5mwB3mPvF4m8HpfMkj0CP7cQlpSGkA6eOuxr0NN8t 3wkkgWtDXcMkK7IZHuIUZ3Fk+Hv5+WuKsqTlG8pqzR+bX+qIkqBTZ97oeUKFgz5AthDjqrj 9MHWEyaAG1KoHiqZDDqLAQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12551327821234229621 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH] RISC-V: Reorganize and rename combine patterns in autovec-opt.md Date: Wed, 20 Sep 2023 15:03:11 +0800 Message-Id: <20230920070311.3472141-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777539170362039363 X-GMAIL-MSGID: 1777539170362039363 This patch reorganize and rename the combine patterns in autovec-opt.md by category. There shouldn't be any functional changes. The current classification includes the following categories: - Combine op + vmerge to cond_op - Combine binop + trunc to narrow_binop - Combine extend + binop to widen_binop - Combine extend + ternop to widen_ternop - Misc combine patterns gcc/ChangeLog: * config/riscv/autovec-opt.md (*not): Move and rename. (*n): Ditto. (*vtrunc): Ditto. (*trunc): Ditto. (*narrow_): Ditto. (*narrow__scalar): Ditto. (*single_widen_mult): Ditto. (*single_widen_mul): Ditto. (*single_widen_mult): Ditto. (*single_widen_mul): Ditto. (*dual_widen_fma): Ditto. (*dual_widen_fma): Ditto. (*single_widen_fma): Ditto. (*single_widen_fma): Ditto. (*dual_fma): Ditto. (*single_fma): Ditto. (*dual_fnma): Ditto. (*dual_widen_fnma): Ditto. (*single_fnma): Ditto. (*single_widen_fnma): Ditto. (*dual_fms): Ditto. (*dual_widen_fms): Ditto. (*single_fms): Ditto. (*single_widen_fms): Ditto. (*dual_fnms): Ditto. (*dual_widen_fnms): Ditto. (*single_fnms): Ditto. (*single_widen_fnms): Ditto. --- gcc/config/riscv/autovec-opt.md | 203 ++++++++++++++------------------ 1 file changed, 91 insertions(+), 112 deletions(-) -- 2.36.3 diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 66c77ad6ebb..46a344407c7 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -58,104 +58,6 @@ } ) -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted second input) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmandnot.mm -;; - vmornot.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*not" - [(set (match_operand:VB_VLS 0 "register_operand" "=vr") - (bitmanip_bitwise:VB_VLS - (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr")) - (match_operand:VB_VLS 1 "register_operand" " vr")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] - { - insn_code icode = code_for_pred_not (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted result) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmnand.mm -;; - vmnor.mm -;; - vmxnor.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*n" - [(set (match_operand:VB_VLS 0 "register_operand" "=vr") - (not:VB_VLS - (any_bitwise:VB_VLS - (match_operand:VB_VLS 1 "register_operand" " vr") - (match_operand:VB_VLS 2 "register_operand" " vr"))))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] - { - insn_code icode = code_for_pred_n (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - -;; ------------------------------------------------------------------------- -;; ---- [INT] Binary narrow shifts. -;; ------------------------------------------------------------------------- -;; Includes: -;; - vnsrl.wv/vnsrl.wx/vnsrl.wi -;; - vnsra.wv/vnsra.wx/vnsra.wi -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*vtrunc" - [(set (match_operand: 0 "register_operand" "=vr,vr") - (truncate: - (any_shiftrt:VWEXTI - (match_operand:VWEXTI 1 "register_operand" " vr,vr") - (any_extend:VWEXTI - (match_operand: 2 "vector_shift_operand" " vr,vk")))))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - insn_code icode = code_for_pred_narrow (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); - DONE; -} - [(set_attr "type" "vnshift") - (set_attr "mode" "")]) - -(define_insn_and_split "*trunc" - [(set (match_operand: 0 "register_operand" "=vr") - (truncate: - (any_shiftrt:VWEXTI - (match_operand:VWEXTI 1 "register_operand" " vr") - (match_operand: 2 "csr_operand" " rK"))))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - operands[2] = gen_lowpart (Pmode, operands[2]); - insn_code icode = code_for_pred_narrow_scalar (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); - DONE; -} - [(set_attr "type" "vnshift") - (set_attr "mode" "")]) - ;; ------------------------------------------------------------------------- ;; ---- Sign-extension for vmv.x.s. ;; ------------------------------------------------------------------------- @@ -574,6 +476,48 @@ } [(set_attr "type" "vector")]) +;; ============================================================================= +;; Combine binop + trunc to narrow_binop +;; ============================================================================= + +;; Combine vsr[la].vv + trunc to vnsr[la].wv +(define_insn_and_split "*narrow_" + [(set (match_operand: 0 "register_operand" "=vr,vr") + (truncate: + (any_shiftrt:VWEXTI + (match_operand:VWEXTI 1 "register_operand" " vr,vr") + (any_extend:VWEXTI + (match_operand: 2 "vector_shift_operand" " vr,vk")))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_narrow (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); + DONE; +} + [(set_attr "type" "vnshift")]) + +;; Combine vsr[la].w[xi] + trunc to vnsr[la].w[xi] +(define_insn_and_split "*narrow__scalar" + [(set (match_operand: 0 "register_operand" "=vr") + (truncate: + (any_shiftrt:VWEXTI + (match_operand:VWEXTI 1 "register_operand" " vr") + (match_operand: 2 "csr_operand" " rK"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + operands[2] = gen_lowpart (Pmode, operands[2]); + insn_code icode = code_for_pred_narrow_scalar (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); + DONE; +} + [(set_attr "type" "vnshift")]) + ;; ============================================================================= ;; Combine extend + binop to widen_binop ;; ============================================================================= @@ -638,7 +582,7 @@ ;; i.e. there is no vwmul.wv instruction. This is a temporary pattern ;; produced by a combine pass and if there is no further combine into ;; vwmul.vv pattern, then fall back to extend pattern and vmul.vv pattern. -(define_insn_and_split "*single_widen_mult" +(define_insn_and_split "*single_widen_mul" [(set (match_operand:VWEXTI 0 "register_operand") (mult:VWEXTI (any_extend:VWEXTI @@ -753,7 +697,7 @@ ;; i.e. there is no vfwmul.wv instruction. This is a temporary pattern ;; produced by a combine pass and if there is no further combine into ;; vfwmul.vv pattern, then fall back to extend pattern and vfmul.vv pattern. -(define_insn_and_split "*single_widen_mult" +(define_insn_and_split "*single_widen_mul" [(set (match_operand:VWEXTF 0 "register_operand") (mult:VWEXTF (float_extend:VWEXTF @@ -868,8 +812,8 @@ ;; Combine extend + ternop to widen_ternop ;; ============================================================================= -;; Combine ext + fma(vmacc,vmadd) to widen_fma (vwmacc) -(define_insn_and_split "*dual_widen_fma" +;; Combine ext + fma(vmacc,vmadd) to widen_fma (vwmacc[u]) +(define_insn_and_split "*dual_widen_fma" [(set (match_operand:VWEXTI 0 "register_operand") (plus:VWEXTI (mult:VWEXTI @@ -938,7 +882,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fma pattern. -(define_insn_and_split "*single_widen_fma" +(define_insn_and_split "*single_widen_fma" [(set (match_operand:VWEXTI 0 "register_operand") (plus:VWEXTI (mult:VWEXTI @@ -966,7 +910,7 @@ [(set_attr "type" "viwmuladd")]) ;; Combine extend + fma to widen_fma (vfwmacc) -(define_insn_and_split "*dual_fma" +(define_insn_and_split "*dual_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") (plus:VWEXTF (mult:VWEXTF @@ -991,7 +935,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fma pattern. -(define_insn_and_split "*single_fma" +(define_insn_and_split "*single_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") (plus:VWEXTF (mult:VWEXTF @@ -1018,7 +962,7 @@ [(set_attr "type" "vfwmuladd")]) ;; Combine extend + fnma to widen_fnma (vfwnmsac) -(define_insn_and_split "*dual_fnma" +(define_insn_and_split "*dual_widen_fnma" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (match_operand:VWEXTF 1 "register_operand") @@ -1043,7 +987,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fnma pattern. -(define_insn_and_split "*single_fnma" +(define_insn_and_split "*single_widen_fnma" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (match_operand:VWEXTF 1 "register_operand") @@ -1070,7 +1014,7 @@ [(set_attr "type" "vfwmuladd")]) ;; Combine extend + fms to widen_fms (vfwmsac) -(define_insn_and_split "*dual_fms" +(define_insn_and_split "*dual_widen_fms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1095,7 +1039,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fms pattern. -(define_insn_and_split "*single_fms" +(define_insn_and_split "*single_widen_fms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1122,7 +1066,7 @@ [(set_attr "type" "vfwmuladd")]) ;; Combine extend + fnms to widen_fnms (vfwnmacc) -(define_insn_and_split "*dual_fnms" +(define_insn_and_split "*dual_widen_fnms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1148,7 +1092,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fnms pattern. -(define_insn_and_split "*single_fnms" +(define_insn_and_split "*single_widen_fnms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1179,7 +1123,7 @@ ;; Misc combine patterns ;; ============================================================================= -;; Combine vlmax neg and UNSPEC_VCOPYSIGN +;; Combine neg + vfsgnj to vfsgnjn (define_insn_and_split "*copysign_neg" [(set (match_operand:VF 0 "register_operand") (neg:VF @@ -1197,3 +1141,38 @@ DONE; } [(set_attr "type" "vector")]) + +;; Combine vmand/vmor + vmnot to vmandnot/vmornot +(define_insn_and_split "*not" + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (bitmanip_bitwise:VB_VLS + (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr")) + (match_operand:VB_VLS 1 "register_operand" " vr")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_not (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); + DONE; + } + [(set_attr "type" "vmalu")]) + +;; Combine vmnot + vmand/vmor/vmxor to vmnand/vmnor/vmxnor +(define_insn_and_split "*n" + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (not:VB_VLS + (any_bitwise:VB_VLS + (match_operand:VB_VLS 1 "register_operand" " vr") + (match_operand:VB_VLS 2 "register_operand" " vr"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_n (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); + DONE; + } + [(set_attr "type" "vmalu")])