diff mbox series

RISC-V: Add FNMS floating-point VLS tests

Message ID	20230919121858.572681-1-juzhe.zhong@rivai.ai
State	Unresolved
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D30EC3858C1F From: Juzhe-Zhong <juzhe.zhong@rivai.ai> To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong <juzhe.zhong@rivai.ai> Subject: [PATCH] RISC-V: Add FNMS floating-point VLS tests Date: Tue, 19 Sep 2023 20:18:58 +0800 Message-Id: <20230919121858.572681-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 Precedence: list Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX
Series	RISC-V: Add FNMS floating-point VLS tests \| RISC-V: Add FNMS floating-point VLS tests

Checks

Context	Check	Description
snail/gcc-patch-check	warning	Git am fail log

Commit Message

juzhe.zhong@rivai.ai Sept. 19, 2023, 12:18 p.m. UTC

  Add tests and committed.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Add FNMS VLS modes tests.
	* gcc.target/riscv/rvv/autovec/vls/fnms-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/fnms-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/fnms-3.c: New test.

---
 .../gcc.target/riscv/rvv/autovec/vls/def.h    |  9 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/fnms-1.c | 31 +++++++++++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/fnms-2.c | 30 ++++++++++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/fnms-3.c | 29 +++++++++++++++++
 4 files changed, 99 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c

diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index d7b721b4e3e..64ef72d3ff4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -485,3 +485,12 @@  typedef double v512df __attribute__ ((vector_size (4096)));
     for (int i = 0; i < NUM; ++i)                                              \
       a[i] = b[i] * c[i] - d[i];                                               \
   }
+
+#define DEF_FNMS_VV(PREFIX, NUM, TYPE)                                         \
+  void __attribute__ ((noinline, noclone))                                     \
+  PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c,  \
+			TYPE *restrict d)                                      \
+  {                                                                            \
+    for (int i = 0; i < NUM; ++i)                                              \
+      a[i] = -(b[i] * c[i]) - d[i];                                            \
+  }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
new file mode 100644
index 00000000000..7fb8884f58c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
@@ -0,0 +1,31 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FNMS_VV (fnms, 2, _Float16)
+DEF_FNMS_VV (fnms, 4, _Float16)
+DEF_FNMS_VV (fnms, 8, _Float16)
+DEF_FNMS_VV (fnms, 16, _Float16)
+DEF_FNMS_VV (fnms, 32, _Float16)
+DEF_FNMS_VV (fnms, 64, _Float16)
+DEF_FNMS_VV (fnms, 128, _Float16)
+DEF_FNMS_VV (fnms, 256, _Float16)
+DEF_FNMS_VV (fnms, 512, _Float16)
+DEF_FNMS_VV (fnms, 1024, _Float16)
+DEF_FNMS_VV (fnms, 2048, _Float16)
+
+/* { dg-final { scan-assembler-times {vfnma[c-d][c-d]\.vv} 11 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
new file mode 100644
index 00000000000..b044061c9d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
@@ -0,0 +1,30 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FNMS_VV (fnms, 2, float)
+DEF_FNMS_VV (fnms, 4, float)
+DEF_FNMS_VV (fnms, 8, float)
+DEF_FNMS_VV (fnms, 16, float)
+DEF_FNMS_VV (fnms, 32, float)
+DEF_FNMS_VV (fnms, 64, float)
+DEF_FNMS_VV (fnms, 128, float)
+DEF_FNMS_VV (fnms, 256, float)
+DEF_FNMS_VV (fnms, 512, float)
+DEF_FNMS_VV (fnms, 1024, float)
+
+/* { dg-final { scan-assembler-times {vfnma[c-d][c-d]\.vv} 10 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
new file mode 100644
index 00000000000..5547bc4c130
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_FNMS_VV (fnms, 2, double)
+DEF_FNMS_VV (fnms, 4, double)
+DEF_FNMS_VV (fnms, 8, double)
+DEF_FNMS_VV (fnms, 16, double)
+DEF_FNMS_VV (fnms, 32, double)
+DEF_FNMS_VV (fnms, 64, double)
+DEF_FNMS_VV (fnms, 128, double)
+DEF_FNMS_VV (fnms, 256, double)
+DEF_FNMS_VV (fnms, 512, double)
+
+/* { dg-final { scan-assembler-times {vfnma[c-d][c-d]\.vv} 9 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */