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[8.43.85.97]) by mx.google.com with ESMTPS id d24-20020a17090648d800b009ad7dcecf03si3798354ejt.327.2023.09.18.05.30.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 05:30:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 11BDE3858417 for ; Mon, 18 Sep 2023 12:30:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id A4C933858D32 for ; Mon, 18 Sep 2023 12:30:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A4C933858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp91t1695040193t3q687ob Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 18 Sep 2023 20:29:52 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: HL//fcJeOHz2KZumPgYkIZmKsVHPMReEplFBSAZZDvjVVUCmDlAkWJcwYmI7u RPDAvDZao0kBgMfpR2fImMkzchUDtpsVeeoMcV7eb18/NDM4VPFqpujTVB+xHJXEflP+7hZ NlDiKmi4/LeVCTeq6n7DLC9JHyQqhclhkL3v0fVAe4lQrEubOi2YuYse2E9sXxOwxeSTGny 4Fd4awCyiI6CBmaEr5mbTGur2Uf50I+dMyDW8/Rl9HDy3ROmDtXSzMZ7iZihnR0gY6kuOnO KA2Z4tBWkDqsRbbP/i5PR16qqPzPuIu2w2HZe4BonVo3oMEbY2gGJaXZgHPKRvs5St5eXJY qdCshq19Md6ffoi3427yOsG3ZI0/uVn/S405VahuB6E5NQKY2ulIgPmEixL2XfriZE2RRcx 2Z61JgOzcLI= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12291535116467123033 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH] RISC-V: Removed misleading comments in testcases Date: Mon, 18 Sep 2023 20:29:51 +0800 Message-Id: <20230918122951.3703638-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777378507769512196 X-GMAIL-MSGID: 1777378507769512196 This patch removed the misleading comments in testcases since we support fold min(int, poly) to constant by this patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629651.html). Thereby the csrr will not appear inside the assembly code, even if there is no support for some VLS vector patterns. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/div-1.c: Removed comments. * gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto. --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 1 - 2 files changed, 2 deletions(-) -- 2.36.3 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c index 40224c69458..e36fa9decfd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c @@ -54,5 +54,4 @@ DEF_OP_VV (div, 256, int64_t, /) DEF_OP_VV (div, 512, int64_t, /) /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ -/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c index b34a349949b..db2295b2dd6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c @@ -54,5 +54,4 @@ DEF_OP_VV (shift, 256, int64_t, <<) DEF_OP_VV (shift, 512, int64_t, <<) /* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 41 } } */ -/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */ /* { dg-final { scan-assembler-not {csrr} } } */