From patchwork Mon Sep 18 03:27:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 141236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp2410772vqi; Sun, 17 Sep 2023 20:28:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHa5ADgeyDCUwRTwk0v0nb+2bZ32zRVWrFg8IOIrMAJYLrOLMDncaig8Eg/1o2r5BJAGxbW X-Received: by 2002:a17:906:30c2:b0:9a9:f2fd:2a2b with SMTP id b2-20020a17090630c200b009a9f2fd2a2bmr6687704ejb.73.1695007690233; Sun, 17 Sep 2023 20:28:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695007690; cv=none; d=google.com; s=arc-20160816; b=0UVocRQwqK9zQdY0uv85JEF43EXfhHhesWfGZQVdQAXMLdBwsvsB6gLYcGGrFUJEXE e3eiijFRFyh2+k/rgUZe9OA+UO3JCDPql0TRtK0i+4le41H9kNxo5Gg6KlSsoOYDdQP3 eVfInq2c8saCYgcgMkOMza2r5CH6zZIm4cezQwsjoncFW024g6hsWIxzOL3+ofOqTIR+ iBenxfUJjQQs/QNH7Xqc3f+3OzhOln9luHSIwwodWmC/2hTlhSAYHW5dH+e4win4BqUi qqict2/qu0hKi/RxBtANTDO0BeYMIU5dMj5Wu5rp/uiP+r5TRqiN48A9IVZrMQBsoCKo WcmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=poAliRkUhklhrpCw37Cbo8f6dBNXcgq3yvgdiEbhpCI=; fh=yqBQmCEeFYB2Wjmf8l8QkV/dOy5iKwSEx/iU/FYQjxU=; b=w3gRvctq1X7ROQ4Uh8zJ4BPC5AxaN1Tun9zmufpjePwPpDsYxY+PyiRT/DbgCeH+Id 3tYzuaYFTRrV/sEXsq+y5VcMgYQfJyMOdsAiUWtL1Ft3q/poIosRliW2PHXp/WE8rk7Y 6BAnb0eQhQYePPKLikg7G2Vw5MKeVcFR+nruskpDEXoGmw6LTWEOMN+EoPu51afErnau VFrXZudlzz70PiCZY8dR5rGnNfw1l2Pdg0gNK88kKrkv6ZNuvSwSPcdvzjOCvX8vZeWq vFotcPMGYpNsFbpbjYrigXruA4h0bWQoQ1vH0dontp3/FlUUI10AdfOBdqBHwHEp5qKz Qwyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=mAQhqVI7; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id z19-20020a170906435300b009a16b635792si7295894ejm.716.2023.09.17.20.28.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Sep 2023 20:28:10 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=mAQhqVI7; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D8C193857B98 for ; Mon, 18 Sep 2023 03:28:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D8C193857B98 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695007688; bh=poAliRkUhklhrpCw37Cbo8f6dBNXcgq3yvgdiEbhpCI=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=mAQhqVI7rWBTK2e72KsYXVkoePhpcSyeFCa2tODe992wDHmyajKOCzcLrAkbD9T1W TswO7hRzGrr43TvL25n3dki7Tkgdpzn1hrj8QS+CfUwmtq43izOo1RYiojlGQqHVBF mqGEtPZ1gJfZD4uF2PqeL9iZy6cIOlcSueWsQgDk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id E3BC83858D32 for ; Mon, 18 Sep 2023 03:27:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E3BC83858D32 X-IronPort-AV: E=McAfee;i="6600,9927,10836"; a="446025051" X-IronPort-AV: E=Sophos;i="6.02,155,1688454000"; d="scan'208";a="446025051" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2023 20:27:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10836"; a="811195791" X-IronPort-AV: E=Sophos;i="6.02,155,1688454000"; d="scan'208";a="811195791" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga008.fm.intel.com with ESMTP; 17 Sep 2023 20:27:15 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id AEB5410056F9; Mon, 18 Sep 2023 11:27:13 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support VLS mode for vec_set Date: Mon, 18 Sep 2023 11:27:11 +0800 Message-Id: <20230918032711.3807244-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777344383541745196 X-GMAIL-MSGID: 1777344383541745196 From: Pan Li This patch would like to add the VLS support vec_set, both INT and FP are included. Give sample code as below: typedef long long vl_t \ __attribute__((vector_size(2 * sizeof (long long)))); vl_t init_vl (vl_t v, unsigned index, unsigned value) { v[index] = value; return v; } Before this patch: init_vl: addi sp,sp,-16 vsetivli zero,2,e64,m1,ta,ma vle64.v v1,0(a1) vse64.v v1,0(sp) slli a4,a2,32 srli a2,a4,29 add a2,sp,a2 slli a3,a3,32 srli a3,a3,32 sd a3,0(a2) vle64.v v1,0(sp) vse64.v v1,0(a0) addi sp,sp,16 jr ra After this patch: init_vl: vsetivli zero,2,e64,m1,ta,ma vle64.v v1,0(a1) slli a3,a3,32 srli a3,a3,32 addi a5,a2,1 vsetvli zero,a5,e64,m1,tu,ma vmv.v.x v2,a3 vslideup.vx v1,v2,a2 vsetivli zero,2,e64,m1,ta,ma vse64.v v1,0(a0) ret Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix. gcc/ChangeLog: * config/riscv/autovec.md: Extend to vls mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: New macros. * gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test. * gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/autovec.md | 4 +-- .../gcc.target/riscv/rvv/autovec/vls/def.h | 18 ++++++++++ .../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++++++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-10.c | 31 ++++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-11.c | 29 +++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-12.c | 21 +++++++++++ .../riscv/rvv/autovec/vls/vec-set-13.c | 20 +++++++++++ .../riscv/rvv/autovec/vls/vec-set-14.c | 19 ++++++++++ .../riscv/rvv/autovec/vls/vec-set-15.c | 18 ++++++++++ .../riscv/rvv/autovec/vls/vec-set-16.c | 21 +++++++++++ .../riscv/rvv/autovec/vls/vec-set-17.c | 20 +++++++++++ .../riscv/rvv/autovec/vls/vec-set-18.c | 19 ++++++++++ .../riscv/rvv/autovec/vls/vec-set-19.c | 18 ++++++++++ .../riscv/rvv/autovec/vls/vec-set-2.c | 33 +++++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-20.c | 20 +++++++++++ .../riscv/rvv/autovec/vls/vec-set-21.c | 19 ++++++++++ .../riscv/rvv/autovec/vls/vec-set-22.c | 18 ++++++++++ .../riscv/rvv/autovec/vls/vec-set-3.c | 31 ++++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++++++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-6.c | 33 +++++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-7.c | 31 ++++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++++++++++++++ .../riscv/rvv/autovec/vls/vec-set-9.c | 33 +++++++++++++++++ 24 files changed, 582 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 01291ad9830..ac680114b5e 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1393,9 +1393,9 @@ (define_expand "select_vl" ;; ------------------------------------------------------------------------- (define_expand "vec_set" - [(match_operand:V 0 "register_operand") + [(match_operand:V_VLS 0 "register_operand") (match_operand: 1 "register_operand") - (match_operand 2 "nonmemory_operand")] + (match_operand 2 "nonmemory_operand")] "TARGET_VECTOR" { /* If we set the first element, emit an v(f)mv.s.[xf]. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 81c4570836b..446eee498de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -266,3 +266,21 @@ typedef double v512df __attribute__ ((vector_size (4096))); for (int i = 0; i < NUM; ++i) \ a[i] = b[i] * CALL (1.0, c[i]); \ } + +#define DEF_VEC_SET_IMM_INDEX(PREFIX, VECTOR, TYPE, INDEX) \ + VECTOR __attribute__ ((noinline, noclone)) \ + PREFIX##_##VECTOR##_##INDEX (VECTOR v, TYPE a) \ + { \ + v[INDEX] = a; \ + \ + return v; \ + } + +#define DEF_VEC_SET_SCALAR_INDEX(PREFIX, VECTOR, TYPE) \ + VECTOR __attribute__ ((noinline, noclone)) \ + PREFIX##_##VECTOR##_##TYPE (VECTOR v, TYPE a, unsigned index) \ + { \ + v[index] = a; \ + \ + return v; \ + } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c new file mode 100644 index 00000000000..d53fdc22162 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048qi, int8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4096qi, int8_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048qi, int8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4096qi, int8_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 12 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c new file mode 100644 index 00000000000..c9242362372 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512sf, float, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024sf, float, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512sf, float, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024sf, float, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]+} 10 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c new file mode 100644 index 00000000000..4ec86789d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256df, double, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512df, double, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256df, double, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512df, double, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]+} 9 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c new file mode 100644 index 00000000000..4436830307b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048qi, int8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4096qi, int8_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[axt][0-9]+} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c new file mode 100644 index 00000000000..037a4a6f71a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024hi, int16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048hi, int16_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[axt][0-9]+} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c new file mode 100644 index 00000000000..4dd58884d79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512si, int32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024si, int32_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c new file mode 100644 index 00000000000..77eeed49a99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256di, int64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512di, int64_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c new file mode 100644 index 00000000000..4f2bb2c7508 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048uqi, uint8_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4096uqi, uint8_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c new file mode 100644 index 00000000000..9376aee2ac2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024uhi, uint16_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048uhi, uint16_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c new file mode 100644 index 00000000000..ade887ea3be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512usi, uint32_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024usi, uint32_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c new file mode 100644 index 00000000000..7106bd936ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256udi, uint64_t) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512udi, uint64_t) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c new file mode 100644 index 00000000000..6132bb4945a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hi, int16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hi, int16_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hi, int16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hi, int16_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 11 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c new file mode 100644 index 00000000000..2da3e3c18a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024hf, _Float16) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048hf, _Float16) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c new file mode 100644 index 00000000000..db2682ad3fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512sf, float) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024sf, float) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c new file mode 100644 index 00000000000..3bb3936c006 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256df, double) +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512df, double) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[axt][0-9]+} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c new file mode 100644 index 00000000000..6080060b60d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512si, int32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024si, int32_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512si, int32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024si, int32_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 10 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c new file mode 100644 index 00000000000..09852f7ca1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256di, int64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512di, int64_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256di, int64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512di, int64_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 9 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c new file mode 100644 index 00000000000..b6a4d1a2c8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uqi, uint8_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4096uqi, uint8_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uqi, uint8_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4096uqi, uint8_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 12 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c new file mode 100644 index 00000000000..11e22db53f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uhi, uint16_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uhi, uint16_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uhi, uint16_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uhi, uint16_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 11 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c new file mode 100644 index 00000000000..d4ce093f201 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512usi, uint32_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024usi, uint32_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512usi, uint32_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024usi, uint32_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 10 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 10 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c new file mode 100644 index 00000000000..4beb2b0b9be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256udi, uint64_t, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512udi, uint64_t, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256udi, uint64_t, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512udi, uint64_t, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 9 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c new file mode 100644 index 00000000000..b59f3f3d121 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_VEC_SET_IMM_INDEX (vec_set, v1hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v4hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v8hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v16hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v32hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v64hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v128hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v256hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v512hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hf, _Float16, 0) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hf, _Float16, 0) + +DEF_VEC_SET_IMM_INDEX (vec_set, v2hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v4hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v8hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v16hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v32hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v64hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v128hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v256hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v512hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hf, _Float16, 1) +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hf, _Float16, 1) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]+} 11 } } */ +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 11 } } */