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[8.43.85.97]) by mx.google.com with ESMTPS id l18-20020aa7c3d2000000b0052a250a9ffasi2609026edr.187.2023.09.14.20.55.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 20:55:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4F93C3847EE8 for ; Fri, 15 Sep 2023 03:34:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 18DF43858436 for ; Fri, 15 Sep 2023 03:33:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 18DF43858436 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgzaS-0002lQ-DT for gcc-patches@gcc.gnu.org; Thu, 14 Sep 2023 23:33:47 -0400 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8DxxPCM0ANl1REoAA--.12426S3; Fri, 15 Sep 2023 11:33:33 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxO9yJ0ANlrFwGAA--.12358S2; Fri, 15 Sep 2023 11:33:30 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng , yala Subject: [PATCH v1] LoongArch: Add floating point conditional move support. Date: Fri, 15 Sep 2023 11:33:03 +0800 Message-Id: <20230915033302.21325-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxO9yJ0ANlrFwGAA--.12358S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj9fXoWfGryxZFyfuF4xArW3tr13GFX_yoW8JFW5Zo WrAFZ8Gw18GrnI93srKrn3JrykXF4jyr4xAFZIvw1rCa1DZry5XF9rGa1Yva43XFnxX34U uFy0gF93Jas7Jw4kl-sFpf9Il3svdjkaLaAFLSUrUUUUbb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY17kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280 aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU7_MaUUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777074305503113468 X-GMAIL-MSGID: 1777074305503113468 gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_expand_conditional_move): Modify the return value type of a function. * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Added floating point conditional transfer implementation code. * config/loongarch/loongarch.md (%3,%2): Define new code_attr. (@movdgr2fr): New template. (@movdfr2gr): Likewise. (@movfr2fcc): Likewise. (@movgr2fcc): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/cmov_ff.c: New test. * gcc.target/loongarch/cmov_fi.c: New test. * gcc.target/loongarch/cmov_if.c: New test. Signed-off-by: yala --- gcc/config/loongarch/loongarch-protos.h | 2 +- gcc/config/loongarch/loongarch.cc | 117 ++++++++++++++++++- gcc/config/loongarch/loongarch.md | 60 ++++++++-- gcc/testsuite/gcc.target/loongarch/cmov_ff.c | 16 +++ gcc/testsuite/gcc.target/loongarch/cmov_fi.c | 15 +++ gcc/testsuite/gcc.target/loongarch/cmov_if.c | 15 +++ 6 files changed, 208 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/cmov_ff.c create mode 100644 gcc/testsuite/gcc.target/loongarch/cmov_fi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/cmov_if.c diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h index 251011c5414..5501fb8da97 100644 --- a/gcc/config/loongarch/loongarch-protos.h +++ b/gcc/config/loongarch/loongarch-protos.h @@ -100,7 +100,7 @@ extern bool loongarch_cfun_has_cprestore_slot_p (void); extern void loongarch_expand_scc (rtx *); extern bool loongarch_expand_vec_cmp (rtx *); extern void loongarch_expand_conditional_branch (rtx *); -extern void loongarch_expand_conditional_move (rtx *); +extern bool loongarch_expand_conditional_move (rtx *); extern void loongarch_expand_conditional_trap (rtx); #endif extern void loongarch_set_return_address (rtx, rtx); diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 845fad5a8e8..5aad5058024 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -5063,7 +5063,42 @@ loongarch_expand_conditional_branch (rtx *operands) /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */ -void +/* iiii: means selecting a fixed point based on fixed point comparison result. + cmp_code is eq/ne: + xor op0 i i + maskeqz + masknez + or + cmp_code is not eq/ne: + slt[u] op0 i i + maskeqz + masknez + or + + iiff: means Selecting a floating point base on fixed point comparison result. + cmp_code is eq/ne: + xor op0 i i + slt[u] op1 + movdgr2fr f, op1 + movfr2fcc fcc, f0 + fsel f, f, f, fcc + cmp_code is not eq/ne: + slt[u] op0 + movdgr2fr f, op0 + movfr2fcc fcc, f + fsel f,f,f,fcc + + ffii: means Selecting a fixed point base on floating point comparison result. + fcmp.cond.{s/d} fcc, f, f + movgr2fr f, i + movgr2fr f, i + fsel f,f,f,fcc + movfr2gr i,f + + ffff: means Selecting a floating point base on floating point comparison + result. + fcmp.cond.{s.d}. */ +bool loongarch_expand_conditional_move (rtx *operands) { enum rtx_code code = GET_CODE (operands[1]); @@ -5071,6 +5106,8 @@ loongarch_expand_conditional_move (rtx *operands) rtx op1 = XEXP (operands[1], 1); rtx op0_extend = op0; rtx op1_extend = op1; + machine_mode cmp_mode = GET_MODE (op0); + machine_mode sel_mode = GET_MODE (operands[2]); /* Record whether operands[2] and operands[3] modes are promoted to word_mode. */ bool promote_p = false; @@ -5097,6 +5134,12 @@ loongarch_expand_conditional_move (rtx *operands) if (code == EQ || code == NE) { op0 = loongarch_zero_if_equal (op0, op1); + + /* Be careful iiff. */ + if (FLOAT_MODE_P (sel_mode)) + loongarch_emit_int_order_test (LTU, NULL, op0, + force_reg (GET_MODE (op0), + const0_rtx), op0); op1 = const0_rtx; } else @@ -5115,7 +5158,8 @@ loongarch_expand_conditional_move (rtx *operands) rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); /* There is no direct support for general conditional GP move involving two registers using SEL. */ - if (INTEGRAL_MODE_P (GET_MODE (operands[2])) + if (INTEGRAL_MODE_P (cmp_mode) + && (INTEGRAL_MODE_P (sel_mode)) && register_operand (operands[2], VOIDmode) && register_operand (operands[3], VOIDmode)) { @@ -5165,11 +5209,72 @@ loongarch_expand_conditional_move (rtx *operands) } else emit_insn (gen_rtx_SET (operands[0], gen_rtx_IOR (mode, temp, temp2))); + + return true; } - else - emit_insn (gen_rtx_SET (operands[0], - gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond, - operands[2], operands[3]))); + /* For ffii, iiff due to movgr2fr, movfr2gr overhead is relatively large, so + we use some compromise. */ + else if (INTEGRAL_MODE_P (cmp_mode) + && (FLOAT_MODE_P (sel_mode)) + && register_operand (operands[2], VOIDmode) + && register_operand (operands[3], VOIDmode)) + { + rtx temp = gen_reg_rtx (sel_mode); + rtx fcc_reg = loongarch_allocate_fcc (FCCmode); + rtx diop0 = convert_to_mode (E_DImode, op0, true); + + /* stl t0 i i-> movgr2fr f0 t0 -> movfr2cf fcc0 f0 -> fsel f f. */ + emit_insn (gen_movdgr2fr (sel_mode, temp, diop0)); + emit_insn (gen_movfr2fcc (sel_mode, fcc_reg, temp)); + + cond = gen_rtx_fmt_ee (code, GET_MODE (fcc_reg), fcc_reg, const0_rtx); + + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), + cond, operands[2], + operands[3]))); + return true; + } + else if (FLOAT_MODE_P (cmp_mode) && (INTEGRAL_MODE_P (sel_mode))) + { + /* movgr2fr f0 i -> movgr2fr f1 i -> fcmp fcc0 f f + -> fsel f3 f0 f1 -> movfr2gr t0 f3. */ + machine_mode dst_mode = GET_MODE (operands[0]); + rtx temp = gen_reg_rtx (E_DFmode); + rtx temp2 = gen_reg_rtx (E_DFmode); + rtx temp3 = gen_reg_rtx (E_DFmode); + + if (CONST_INT_P (operands[2])) + operands[2] = copy_to_mode_reg (dst_mode, operands[2]); + + if (CONST_INT_P (operands[3])) + operands[3] = copy_to_mode_reg (dst_mode, operands[3]); + + if (GET_MODE (operands[2]) != E_DImode) + operands[2] = convert_to_mode (E_DImode, operands[2], false); + + if (GET_MODE (operands[3]) != E_DImode) + operands[3] = convert_to_mode (E_DImode, operands[3], false); + + emit_insn (gen_movdgr2frdf (temp2, operands[2])); + emit_insn (gen_movdgr2frdf (temp3, operands[3])); + emit_insn (gen_rtx_SET (temp, + gen_rtx_IF_THEN_ELSE (E_DFmode, cond, + temp2, temp3))); + emit_insn (gen_movdfr2gr (GET_MODE (operands[0]), operands[0], temp)); + + return true; + } + else if (FLOAT_MODE_P (cmp_mode) && FLOAT_MODE_P (sel_mode)) + { + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), + cond, operands[2], + operands[3]))); + return true; + } + + return false; } /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 4fcb6d781d5..158480ca2a4 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -30,7 +30,12 @@ (define_c_enum "unspec" [ UNSPEC_LOAD_HIGH UNSPEC_STORE_WORD UNSPEC_MOVGR2FRH + UNSPEC_MOVGR2FR UNSPEC_MOVFRH2GR + UNSPEC_MOVFR2GR + UNSPEC_MOVFCC2GR + UNSPEC_MOVGR2FCC + UNSPEC_MOVFR2FCC ;; Floating point unspecs. UNSPEC_FRINT @@ -295,6 +300,7 @@ (define_attr "type" ;; D2I float to integer (DF to SI/DI) ;; D2S double to float single ;; S2D float single to double +;; C2D fcc to DI (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D" (const_string "unknown")) @@ -559,6 +565,7 @@ (define_code_attr fcond [(unordered "cun") ;; The sel mnemonic to use depending on the condition test. (define_code_attr sel [(eq "masknez") (ne "maskeqz")]) +(define_code_attr fsel_invert [(eq "%2,%3") (ne "%3,%2")]) (define_code_attr selinv [(eq "maskeqz") (ne "masknez")]) ;; Iterator and attributes for floating-point to fixed-point conversion @@ -2178,12 +2185,12 @@ (define_insn "*sel_using_" (define_insn "*sel" [(set (match_operand:ANYF 0 "register_operand" "=f") (if_then_else:ANYF - (ne:FCC (match_operand:FCC 1 "register_operand" "z") + (equality_op:FCC (match_operand:FCC 1 "register_operand" "z") (const_int 0)) (match_operand:ANYF 2 "reg_or_0_operand" "f") (match_operand:ANYF 3 "reg_or_0_operand" "f")))] "" - "fsel\t%0,%3,%2,%1" + "fsel\t%0,,%1" [(set_attr "type" "condmove") (set_attr "mode" "")]) @@ -2196,11 +2203,10 @@ (define_expand "movcc" (match_operand:GPR 3 "reg_or_0_operand")])))] "TARGET_COND_MOVE_INT" { - if (!INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0)))) + if (loongarch_expand_conditional_move (operands)) + DONE; + else FAIL; - - loongarch_expand_conditional_move (operands); - DONE; }) (define_expand "movcc" @@ -2210,11 +2216,11 @@ (define_expand "movcc" (match_operand:ANYF 3 "reg_or_0_operand")])))] "TARGET_COND_MOVE_FLOAT" { - if (!FLOAT_MODE_P (GET_MODE (XEXP (operands[1], 0)))) - FAIL; - loongarch_expand_conditional_move (operands); - DONE; + if (loongarch_expand_conditional_move (operands)) + DONE; + else + FAIL; }) (define_insn "lu32i_d" @@ -2447,6 +2453,15 @@ (define_insn "movgr2frh" [(set_attr "move_type" "mgtf") (set_attr "mode" "")]) +(define_insn "@movdgr2fr" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (unspec:ANYF [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_MOVGR2FR))] + "TARGET_DOUBLE_FLOAT" + "movgr2fr.d\t%0,%1" + [(set_attr "move_type" "mgtf") + (set_attr "mode" "")]) + ;; Move high word of operand 1 to operand 0 using movfrh2gr.s. (define_insn "movfrh2gr" [(set (match_operand: 0 "register_operand" "=r") @@ -2457,6 +2472,31 @@ (define_insn "movfrh2gr" [(set_attr "move_type" "mftg") (set_attr "mode" "")]) +(define_insn "@movdfr2gr" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec:GPR [(match_operand:DF 1 "register_operand" "f")] + UNSPEC_MOVFR2GR))] + "TARGET_DOUBLE_FLOAT" + "movfr2gr.d\t%0,%1" + [(set_attr "move_type" "mftg") + (set_attr "mode" "")]) + +(define_insn "@movfr2fcc" + [(set (match_operand:FCC 0 "register_operand" "=z") + (unspec:FCC [(match_operand:ANYF 1 "register_operand" "f")] + UNSPEC_MOVFR2FCC))] + "TARGET_HARD_FLOAT" + "movfr2cf\t%0,%1" + [(set_attr "mode" "")]) + +(define_insn "@movgr2fcc" + [(set (match_operand:FCC 0 "register_operand" "=z") + (unspec:FCC [(match_operand:GPR 1 "register_operand" "r")] + UNSPEC_MOVGR2FCC))] + "TARGET_HARD_FLOAT" + "movgr2cf\t%0,%1" + [(set_attr "mode" "")]) + ;; Expand in-line code to clear the instruction cache between operand[0] and ;; operand[1]. diff --git a/gcc/testsuite/gcc.target/loongarch/cmov_ff.c b/gcc/testsuite/gcc.target/loongarch/cmov_ff.c new file mode 100644 index 00000000000..c49a20f23a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/cmov_ff.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mdouble-float" } */ +/* { dg-final { scan-assembler "test:.*fcmp.*fsel.*" } } */ + +extern void foo_ff (float *, float *, float *, float *); + +float +test (void) +{ + float a, b; + float c, d, out; + foo_ff (&a, &b, &c, &d); + out = a > b ? c : d; + return out; +} + diff --git a/gcc/testsuite/gcc.target/loongarch/cmov_fi.c b/gcc/testsuite/gcc.target/loongarch/cmov_fi.c new file mode 100644 index 00000000000..07838dad748 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/cmov_fi.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mdouble-float" } */ +/* { dg-final { scan-assembler "test:.*movgr2fr.*movgr2fr.*fsel.*movfr2gr.*" } } */ + +extern void foo_fi (float *, float *, int *, int *); + +int +test (void) +{ + float a, b; + int c, d, out; + foo_fi (&a, &b, &c, &d); + out = a > b ? c : d; + return out; +} diff --git a/gcc/testsuite/gcc.target/loongarch/cmov_if.c b/gcc/testsuite/gcc.target/loongarch/cmov_if.c new file mode 100644 index 00000000000..8da11bc90a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/cmov_if.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mdouble-float" } */ +/* { dg-final { scan-assembler "test:.*movfr2cf.*fsel.*" } } */ + +extern void foo_if (int *, int *, float *, float *); + +float +test (void) +{ + int a, b; + float c, d, out; + foo_if (&a, &b, &c, &d); + out = a == b ? c : d; + return out; +}