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[8.43.85.97]) by mx.google.com with ESMTPS id o9-20020a1709062e8900b009a5a4b6d098si824240eji.1052.2023.09.14.00.52.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 00:52:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C91C63858291 for ; Thu, 14 Sep 2023 07:52:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 7E9C03858C3A for ; Thu, 14 Sep 2023 07:52:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7E9C03858C3A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp69t1694677935te3b2zih Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 14 Sep 2023 15:52:14 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 2w1wQVt6itTZqWKeP4xoun29vN4XLZAW1Exx06rAhBNeUU4wyN/D0inaY31AB 5V+CNy3lRttv8GSZYmHRfVikaRpB6b7x6dX2HZxqeM/pbn08pYB9l36+IDwAmQJwVz3o32f 9pTWiM32fDgPAwe2Rn6HUwls5ZUzZ0LR70473WiXrstDKympjRF0HkNz8DCTNA3kdb4uyYU 8OfWPRro9STok7RC5iT25AfzfRXGb3l53tNnHSfyikzv/pZ4Po1+wYRHxsEYKbMgddVrNn8 5c3ai8z75PhBrV09TUM+LA7PJw9cjvExSHwX/4ex8rsGtH61CiCbjZjdPbU5lAPRo93v2yU eBkFT45qxxzU/L0/82kjrqy/2WWMebuMTmHc1P1PnFVlVyVexc6tjApNvD8K13E6WKcQvvt X-QQ-GoodBg: 2 X-BIZMAIL-ID: 9865466039847225114 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg Date: Thu, 14 Sep 2023 15:52:13 +0800 Message-Id: <20230914075213.3213806-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776998653255503988 X-GMAIL-MSGID: 1776998653255503988 update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp. This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE update v2 -> v3: Remove redundant format. PR target/111395 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE. (vector_insn_info::global_merge): Ditto. (vector_insn_info::get_avl_or_vl_reg): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/fortran/pr111395.f90: New test. * gcc.target/riscv/rvv/rvv-fortran.exp: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 28 +++++++----- .../gcc.target/riscv/rvv/fortran/pr111395.f90 | 41 +++++++++++++++++ .../gcc.target/riscv/rvv/rvv-fortran.exp | 45 +++++++++++++++++++ 3 files changed, 103 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index f81361c4ccd..8ec54092a48 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1652,6 +1652,8 @@ avl_info::operator== (const avl_info &other) const /* Handle VLMAX AVL. */ if (vlmax_avl_p (m_value)) return vlmax_avl_p (other.get_value ()); + if (vlmax_avl_p (other.get_value ())) + return false; /* If any source is undef value, we think they are not equal. */ if (!m_source || !other.get_source ()) @@ -2258,6 +2260,18 @@ vector_insn_info::global_merge (const vector_insn_info &merge_info, new_info.set_avl_source (first_set); } + /* Make sure VLMAX AVL always has a set_info the get VL. */ + if (vlmax_avl_p (new_info.get_avl ())) + { + if (this->get_avl_source ()) + new_info.set_avl_source (this->get_avl_source ()); + else + { + gcc_assert (merge_info.get_avl_source ()); + new_info.set_avl_source (merge_info.get_avl_source ()); + } + } + new_info.fuse_sew_lmul (*this, merge_info); new_info.fuse_tail_policy (*this, merge_info); new_info.fuse_mask_policy (*this, merge_info); @@ -2274,9 +2288,6 @@ vector_insn_info::get_avl_or_vl_reg (void) const if (!vlmax_avl_p (get_avl ())) return get_avl (); - if (get_avl_source ()) - return get_avl_reg_rtx (); - rtx_insn *rinsn = get_insn ()->rtl (); if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn)) { @@ -2288,14 +2299,9 @@ vector_insn_info::get_avl_or_vl_reg (void) const return vl; } - /* A DIRTY (polluted EMPTY) block if: - - get_insn is scalar move (no AVL or VL operand). - - get_avl_source is null (no def in the current DIRTY block). - Then we trace the previous insn which must be the insn - already inserted in Phase 2 to get the VL operand for VLMAX. */ - rtx_insn *prev_rinsn = PREV_INSN (rinsn); - gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn)); - return ::get_vl (prev_rinsn); + /* We always has avl_source if it is VLMAX AVL. */ + gcc_assert (get_avl_source ()); + return get_avl_reg_rtx (); } bool diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 new file mode 100644 index 00000000000..71253fe6bc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 @@ -0,0 +1,41 @@ +! { dg-do compile } +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" } + +MODULE a + REAL b +CONTAINS + SUBROUTINE c(d,KTE) + REAL,DIMENSION(KTE) :: d,e,f,g + REAL,DIMENSION(KTE) :: h + i : DO j=1,b + z=k + DO l=m,n + IF(o>=p)THEN + IF(laf)THEN + DO l=m,n + d=h + ENDDO + ENDIF + END SUBROUTINE c +END MODULE a diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp new file mode 100644 index 00000000000..88d82281d43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp @@ -0,0 +1,45 @@ +# Copyright (C) 2023-2023 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a RISC-V target. +if { ![istarget riscv*-*-*] } then { + return +} + +# Make sure there is a fortran compiler to test. +if { ![check_no_compiler_messages fortran_available assembly { +! Fortran +program P + stop +end program P +} ""] } { + return +} + +# Load support procs. +load_lib gfortran-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +gfortran-dg-runtest [lsort \ + [glob -nocomplain $srcdir/$subdir/fortran/*.\[fF\]{,90,95,03,08} ] ] "" "" + +# All done. +dg-finish