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[8.43.85.97]) by mx.google.com with ESMTPS id i7-20020aa7c707000000b0052576324490si9238772edq.157.2023.09.12.08.30.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 08:30:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=iQU+hgVc; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4EDA838293EE for ; Tue, 12 Sep 2023 15:27:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4EDA838293EE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694532448; bh=LeYyR2ZrUwKKa8ygOny3vB4VWcKHAlvHBpS8GDIKCnk=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=iQU+hgVcsTqY5kWo+/FcWmuRVGKeweLLpKRkCrCCzXFGBrlf8BKqJ0IbtWkFwyryR M9sdLtzTxBqeAodHtwc2v6J+Y6HJu1XRYJIZR6dxbujC03Knpn4VEDjotutb3axVPX AqQJEIxcW4Mk57XM7ID2mW83ne44buwBpaQaOd8w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 3C8AD3853570 for ; Tue, 12 Sep 2023 15:25:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3C8AD3853570 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21BC81007; Tue, 12 Sep 2023 08:26:17 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 782D43F738; Tue, 12 Sep 2023 08:25:39 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 02/19] aarch64: Avoid a use of callee_offset Date: Tue, 12 Sep 2023 16:25:12 +0100 Message-Id: <20230912152529.3322336-3-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912152529.3322336-1-richard.sandiford@arm.com> References: <20230912152529.3322336-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-25.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776846237761473301 X-GMAIL-MSGID: 1776846237761473301 When we emit the frame chain, i.e. when we reach Here in this statement of aarch64_expand_prologue: if (emit_frame_chain) { // Here ... } the stack is in one of two states: - We've allocated up to the frame chain, but no more. - We've allocated the whole frame, and the frame chain is within easy reach of the new SP. The offset of the frame chain from the current SP is available in aarch64_frame as callee_offset. It is also available as the chain_offset local variable, where the latter is calculated from other data. (However, chain_offset is not always equal to callee_offset when !emit_frame_chain, so chain_offset isn't redundant.) In c600df9a4060da3c6121ff4d0b93f179eafd69d1 I switched to using chain_offset for the initialisation of the hard frame pointer: aarch64_add_offset (Pmode, hard_frame_pointer_rtx, - stack_pointer_rtx, callee_offset, + stack_pointer_rtx, chain_offset, tmp1_rtx, tmp0_rtx, frame_pointer_needed); But the later REG_CFA_ADJUST_CFA handling still used callee_offset. I think the difference is harmless, but it's more logical for the CFA note to be in sync, and it's more convenient for later patches if it uses chain_offset. gcc/ * config/aarch64/aarch64.cc (aarch64_expand_prologue): Use chain_offset rather than callee_offset. --- gcc/config/aarch64/aarch64.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index b91f77d7b1f..9fb94623693 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -10034,7 +10034,6 @@ aarch64_expand_prologue (void) poly_int64 initial_adjust = frame.initial_adjust; HOST_WIDE_INT callee_adjust = frame.callee_adjust; poly_int64 final_adjust = frame.final_adjust; - poly_int64 callee_offset = frame.callee_offset; poly_int64 sve_callee_adjust = frame.sve_callee_adjust; poly_int64 below_hard_fp_saved_regs_size = frame.below_hard_fp_saved_regs_size; @@ -10147,8 +10146,7 @@ aarch64_expand_prologue (void) implicit. */ if (!find_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX)) { - rtx src = plus_constant (Pmode, stack_pointer_rtx, - callee_offset); + rtx src = plus_constant (Pmode, stack_pointer_rtx, chain_offset); add_reg_note (insn, REG_CFA_ADJUST_CFA, gen_rtx_SET (hard_frame_pointer_rtx, src)); }