From patchwork Tue Sep 12 15:25:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 138268 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9ecd:0:b0:3f2:4152:657d with SMTP id t13csp493497vqx; Tue, 12 Sep 2023 08:38:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGkoI9VBw95KGtH6XbzjfFMsegONRHKhytENRzV+6b9SJBv0QDG/aBNtGZziIJrgbiWUA9X X-Received: by 2002:a17:906:5a6d:b0:9a2:26e4:a5e9 with SMTP id my45-20020a1709065a6d00b009a226e4a5e9mr11496006ejc.0.1694533080128; Tue, 12 Sep 2023 08:38:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694533080; cv=none; d=google.com; s=arc-20160816; b=wdvPm8cUx2uR/iviBz+lrI9eQuyWC1CFUDOV7lZhzKU3v6QjeI0TloFKq0VVVV7JAt 4ZEvg+sorcd6FwmYJzo5RYgcXQS2AvU8sJo9QFJrsrjnhCHkvDlK777awNjklwGJ1N7/ NxzDqb+vHW0tDq8Pi9RUq6BJnxfEBibMJsM3KT+4V1VCjSG94hWZKNS27A81dgWBiTJG gSxjiMbj++uzXC13/gbOy69Y6mmBXKyJ/WvzNw6TWWHYIPSxmjKE7HpZ7Fn1AcpsqfW7 5JLKpTAKTbox+GStgUTLWBtRzVSD++YtGpYVqWA/Pv78igeETpx3hjRUnmPUJayORZj4 dFBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=kUSEvo+LVXKPwnnu/TIDi5igGci+X4ZXCDCcv/hmZ6U=; fh=C4nEn4uRKApr1WsFtLyJD8L5BeRuRc+JFyqoopFjd9M=; b=LAtAhcIjvqQLNdAcefABIfW8P10yO6IF8Fhu4nvMlfGI6LYfyUTFoPHgRQoQpWGAB4 ZA/yZL6r+YB+FXgPu1hLPmU5bFeVhNGiPgYlUi7dn6/DcAPRwde/4C1kfOKvbMeXwayy /UHlhOnEXXjlsGooZosxZWNELTM/ZWqnElCIiGO78eV9oVt6TKk5KkowjqiNmwCfKaVs LL93AQnNiZz4u0t/ZVOWbB4AzMA1MDpSMh9F9U5Fmk8j2Fmn7L/J17D/UgbYQ5QiyU88 Us45/OMKIITpKkRkwjxkEuODjDrFwqzOMIsaTp5DS7LO8VuwFA6DQsG1O7Mp4yeGEiyJ 7BVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=kL5xQQ8j; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id p7-20020a170906b20700b009a210885fb0si9239013ejz.852.2023.09.12.08.37.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 08:38:00 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=kL5xQQ8j; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3BD3E395563C for ; Tue, 12 Sep 2023 15:30:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3BD3E395563C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694532614; bh=kUSEvo+LVXKPwnnu/TIDi5igGci+X4ZXCDCcv/hmZ6U=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=kL5xQQ8jfinoI027qOyqxMMeT5iMtK6qysDuiKFemgY/1OpphdZDt0EWmlzYkF617 XvVyU9HIHSmDcMqw86sQKJHcNgBLSNpQSwmYjoRcCkbigWZ19S1TXKHZKOonPyhBGq Tpc3SD7uTitjZNo9c2UJwU6sjRP4o5dFhplKPAEs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id D4B2F3853D20 for ; Tue, 12 Sep 2023 15:25:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D4B2F3853D20 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ED648C15; Tue, 12 Sep 2023 08:26:27 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4FDD53F738; Tue, 12 Sep 2023 08:25:50 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 18/19] aarch64: Remove below_hard_fp_saved_regs_size Date: Tue, 12 Sep 2023 16:25:28 +0100 Message-Id: <20230912152529.3322336-19-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912152529.3322336-1-richard.sandiford@arm.com> References: <20230912152529.3322336-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-24.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776846718998368072 X-GMAIL-MSGID: 1776846718998368072 After previous patches, it's no longer necessary to store saved_regs_size and below_hard_fp_saved_regs_size in the frame info. All measurements instead use the top or bottom of the frame as reference points. gcc/ * config/aarch64/aarch64.h (aarch64_frame::saved_regs_size) (aarch64_frame::below_hard_fp_saved_regs_size): Delete. * config/aarch64/aarch64.cc (aarch64_layout_frame): Update accordingly. --- gcc/config/aarch64/aarch64.cc | 45 ++++++++++++++++------------------- gcc/config/aarch64/aarch64.h | 7 ------ 2 files changed, 21 insertions(+), 31 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 3c7c476c4c6..51e57370807 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -8569,9 +8569,8 @@ aarch64_layout_frame (void) /* OFFSET is now the offset of the hard frame pointer from the bottom of the callee save area. */ - frame.below_hard_fp_saved_regs_size = offset - frame.bytes_below_saved_regs; - bool saves_below_hard_fp_p - = maybe_ne (frame.below_hard_fp_saved_regs_size, 0); + auto below_hard_fp_saved_regs_size = offset - frame.bytes_below_saved_regs; + bool saves_below_hard_fp_p = maybe_ne (below_hard_fp_saved_regs_size, 0); gcc_assert (!saves_below_hard_fp_p || (frame.sve_save_and_probe != INVALID_REGNUM && known_eq (frame.reg_offset[frame.sve_save_and_probe], @@ -8641,9 +8640,8 @@ aarch64_layout_frame (void) offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); - frame.saved_regs_size = offset - frame.bytes_below_saved_regs; - gcc_assert (known_eq (frame.saved_regs_size, - frame.below_hard_fp_saved_regs_size) + auto saved_regs_size = offset - frame.bytes_below_saved_regs; + gcc_assert (known_eq (saved_regs_size, below_hard_fp_saved_regs_size) || (frame.hard_fp_save_and_probe != INVALID_REGNUM && known_eq (frame.reg_offset[frame.hard_fp_save_and_probe], frame.bytes_below_hard_fp))); @@ -8652,7 +8650,7 @@ aarch64_layout_frame (void) The saving of the bottommost register counts as an implicit probe, which allows us to maintain the invariant described in the comment at expand_prologue. */ - gcc_assert (crtl->is_leaf || maybe_ne (frame.saved_regs_size, 0)); + gcc_assert (crtl->is_leaf || maybe_ne (saved_regs_size, 0)); offset += get_frame_size (); offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); @@ -8709,7 +8707,7 @@ aarch64_layout_frame (void) HOST_WIDE_INT const_size, const_below_saved_regs, const_above_fp; HOST_WIDE_INT const_saved_regs_size; - if (known_eq (frame.saved_regs_size, 0)) + if (known_eq (saved_regs_size, 0)) frame.initial_adjust = frame.frame_size; else if (frame.frame_size.is_constant (&const_size) && const_size < max_push_offset @@ -8722,7 +8720,7 @@ aarch64_layout_frame (void) frame.callee_adjust = const_size; } else if (frame.bytes_below_saved_regs.is_constant (&const_below_saved_regs) - && frame.saved_regs_size.is_constant (&const_saved_regs_size) + && saved_regs_size.is_constant (&const_saved_regs_size) && const_below_saved_regs + const_saved_regs_size < 512 /* We could handle this case even with data below the saved registers, provided that that data left us with valid offsets @@ -8741,8 +8739,7 @@ aarch64_layout_frame (void) frame.initial_adjust = frame.frame_size; } else if (saves_below_hard_fp_p - && known_eq (frame.saved_regs_size, - frame.below_hard_fp_saved_regs_size)) + && known_eq (saved_regs_size, below_hard_fp_saved_regs_size)) { /* Frame in which all saves are SVE saves: @@ -8764,7 +8761,7 @@ aarch64_layout_frame (void) [save SVE registers relative to SP] sub sp, sp, bytes_below_saved_regs */ frame.callee_adjust = const_above_fp; - frame.sve_callee_adjust = frame.below_hard_fp_saved_regs_size; + frame.sve_callee_adjust = below_hard_fp_saved_regs_size; frame.final_adjust = frame.bytes_below_saved_regs; } else @@ -8779,7 +8776,7 @@ aarch64_layout_frame (void) [save SVE registers relative to SP] sub sp, sp, bytes_below_saved_regs */ frame.initial_adjust = frame.bytes_above_hard_fp; - frame.sve_callee_adjust = frame.below_hard_fp_saved_regs_size; + frame.sve_callee_adjust = below_hard_fp_saved_regs_size; frame.final_adjust = frame.bytes_below_saved_regs; } @@ -9985,17 +9982,17 @@ aarch64_epilogue_uses (int regno) | local variables | <-- frame_pointer_rtx | | +-------------------------------+ - | padding | \ - +-------------------------------+ | - | callee-saved registers | | frame.saved_regs_size - +-------------------------------+ | - | LR' | | - +-------------------------------+ | - | FP' | | - +-------------------------------+ |<- hard_frame_pointer_rtx (aligned) - | SVE vector registers | | \ - +-------------------------------+ | | below_hard_fp_saved_regs_size - | SVE predicate registers | / / + | padding | + +-------------------------------+ + | callee-saved registers | + +-------------------------------+ + | LR' | + +-------------------------------+ + | FP' | + +-------------------------------+ <-- hard_frame_pointer_rtx (aligned) + | SVE vector registers | + +-------------------------------+ + | SVE predicate registers | +-------------------------------+ | dynamic allocation | +-------------------------------+ diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 8fcebeb5206..d74e9116fc5 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -776,18 +776,11 @@ struct GTY (()) aarch64_frame STACK_BOUNDARY. */ HOST_WIDE_INT saved_varargs_size; - /* The size of the callee-save registers with a slot in REG_OFFSET. */ - poly_int64 saved_regs_size; - /* The number of bytes between the bottom of the static frame (the bottom of the outgoing arguments) and the bottom of the register save area. This value is always a multiple of STACK_BOUNDARY. */ poly_int64 bytes_below_saved_regs; - /* The size of the callee-save registers with a slot in REG_OFFSET that - are saved below the hard frame pointer. */ - poly_int64 below_hard_fp_saved_regs_size; - /* The number of bytes between the bottom of the static frame (the bottom of the outgoing arguments) and the hard frame pointer. This value is always a multiple of STACK_BOUNDARY. */