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dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1694402627tx6ifph4 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 11 Sep 2023 11:23:46 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: znfcQSa1hKayXJDJSravcOZdHYP8DOdluqYPe/IZZ1pjVBsUb/EF0mFG6qdU7 +C04PiTlxXC006St+paELU44iKOqZ/wCQn4uvVljGxLtaUuMUrE+G0XETo9tr8G+/qWKo/7 H7l6uEX6JIkdqI26xWqR3HyuFsIKV0BJ8jPXL/dM9H43XtMys98NsUoAOqOW4R7GhFIABQ6 SbjCkCjYcY2SriXx7YiVDehRoZNgvfrwQQ+h46t41KIiAsqeyEQQzyeJbAnBCsnXzUdXQes 8K4Tlg8Yzj7xz2DlnzoRo0dBrKYWHqwsFNTpE6gk7sKujeK7w8DHvRjHe6AtcLhxym/gQaH qNGKy0F8jXOrY1jL6hYJXsv2NNvXHJ4lofm7Tp6Ar1PxTdfzvu9ziRU3vmL/4hXjX41iP1F tD/aia/rb2Y= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 16526217130647528629 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Subject: [Committed] RISC-V: Add missing VLS mask bool mode reg -> reg patterns Date: Mon, 11 Sep 2023 11:23:43 +0800 Message-Id: <20230911032343.2482218-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, Juzhe-Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776709970990830250 X-GMAIL-MSGID: 1776709970990830250 Committed. gcc/ChangeLog: * config/riscv/autovec-vls.md (*mov_vls): New pattern. * config/riscv/vector-iterators.md: New iterator --- gcc/config/riscv/autovec-vls.md | 8 ++++++++ gcc/config/riscv/vector-iterators.md | 15 +++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index d208b418e5f..6f48f7d6232 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -148,6 +148,14 @@ [(set_attr "type" "vmov") (set_attr "mode" "")]) +(define_insn "*mov_vls" + [(set (match_operand:VLSB 0 "register_operand" "=vr") + (match_operand:VLSB 1 "register_operand" " vr"))] + "TARGET_VECTOR" + "vmv1r.v\t%0,%1" + [(set_attr "type" "vmov") + (set_attr "mode" "")]) + (define_expand "movmisalign" [(set (match_operand:VLS 0 "nonimmediate_operand") (match_operand:VLS 1 "general_operand"))] diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a98ed9fcbb6..5694c0c8f37 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2425,6 +2425,21 @@ (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")]) +(define_mode_iterator VLSB [ + (V1BI "TARGET_VECTOR_VLS") + (V2BI "TARGET_VECTOR_VLS") + (V4BI "TARGET_VECTOR_VLS") + (V8BI "TARGET_VECTOR_VLS") + (V16BI "TARGET_VECTOR_VLS") + (V32BI "TARGET_VECTOR_VLS") + (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")]) + ;; VLS modes that has NUNITS < 32. (define_mode_iterator VLS_AVL_IMM [ (V1QI "TARGET_VECTOR_VLS")