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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q7-20020a056402032700b0052e1af10c51si2653906edw.236.2023.09.08.21.48.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 21:48:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DD2B53865C27 for ; Sat, 9 Sep 2023 04:39:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (unknown [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 7EA5D3858D1E for ; Sat, 9 Sep 2023 04:39:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7EA5D3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp86t1694234296t3ysfuav Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 09 Sep 2023 12:38:15 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: cbck7jzG4warZJB5x06z0M7ZCjS4A/Zin2KG4f/j+qAHWZs9fiiuMM0vXxxLD a7E4P6npPiDSfQdHoCXuF7Mko5IwcohXDZkQa8gsnASRhAuwtmIGHPw2EnqW/5L5eoXzhqj LclG1Ry0opDam7ATgjQjW4oiqm8T4nZQWgwS348XEb+XgsJFuRqV0MIphSlKmtIPqQ5pdU8 ZYDF3pTV7Oj9LjOTTlVCPGr2TTk4hfa6o8qEkJ5EdYuBKxtYvA536dEEByI/x02tyoH36Ut kVgaaO/rN8s7VvRPEQ+lencPoUx/kfvsoGa4InaRJFwNzAhhzxHv9gWkOeNEh4YQV8XgXHm FagTcbxqRPhgxOkO4vf5z7bXvQworHWnotFznan4o3EGEK0WmGw9BIrh2KSG8tFNGq26YOV X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12426072705033237263 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311] Date: Sat, 9 Sep 2023 12:38:14 +0800 Message-Id: <20230909043814.2002924-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, Juzhe-Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776534040066861945 X-GMAIL-MSGID: 1776534040066861945 This patch add VLS modes VEC_PERM support which fix these following FAILs in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311: FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized "BIT_FIELD_REF" 0 FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized "BIT_INSERT_EXPR" 0 FAIL: gcc.dg/tree-ssa/forwprop-41.c scan-tree-dump-times optimized "BIT_FIELD_REF" 0 FAIL: gcc.dg/tree-ssa/forwprop-41.c scan-tree-dump-times optimized "BIT_INSERT_EXPR" 1 These FAILs are fixed after this patch. gcc/ChangeLog: * config/riscv/autovec-vls.md (*mov_vls): New pattern. * config/riscv/autovec.md: Ditto. * config/riscv/riscv-protos.h (cmp_lmul_le_one): New function. (cmp_lmul_gt_one): Ditto * config/riscv/riscv-v.cc (cmp_lmul_le_one): Ditto. (cmp_lmul_gt_one): Ditto. * config/riscv/riscv.cc (riscv_print_operand): Allow VLS modes. (riscv_vectorize_vec_perm_const): Ditto. * config/riscv/vector-iterators.md: Add VLS modes. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/compress-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-7.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-7.c: New test. --- gcc/config/riscv/autovec-vls.md | 8 + gcc/config/riscv/autovec.md | 6 +- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-v.cc | 22 ++ gcc/config/riscv/riscv.cc | 4 +- gcc/config/riscv/vector-iterators.md | 304 +++++++++++++++++- gcc/config/riscv/vector.md | 302 ++++++++--------- .../riscv/rvv/autovec/partial/slp-1.c | 2 +- .../riscv/rvv/autovec/partial/slp-16.c | 2 +- .../riscv/rvv/autovec/partial/slp-17.c | 2 +- .../riscv/rvv/autovec/partial/slp-3.c | 2 +- .../riscv/rvv/autovec/partial/slp-5.c | 2 +- .../riscv/rvv/autovec/vls/compress-1.c | 6 + .../riscv/rvv/autovec/vls/compress-2.c | 7 + .../riscv/rvv/autovec/vls/compress-3.c | 7 + .../riscv/rvv/autovec/vls/compress-4.c | 7 + .../riscv/rvv/autovec/vls/compress-5.c | 6 + .../riscv/rvv/autovec/vls/compress-6.c | 6 + .../riscv/rvv/autovec/vls/merge-1.c | 6 + .../riscv/rvv/autovec/vls/merge-2.c | 6 + .../riscv/rvv/autovec/vls/merge-3.c | 6 + .../riscv/rvv/autovec/vls/merge-4.c | 6 + .../riscv/rvv/autovec/vls/merge-5.c | 6 + .../riscv/rvv/autovec/vls/merge-6.c | 6 + .../riscv/rvv/autovec/vls/merge-7.c | 6 + .../gcc.target/riscv/rvv/autovec/vls/perm-1.c | 6 + .../gcc.target/riscv/rvv/autovec/vls/perm-2.c | 6 + .../gcc.target/riscv/rvv/autovec/vls/perm-3.c | 6 + .../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 8 + .../gcc.target/riscv/rvv/autovec/vls/perm-5.c | 6 + .../gcc.target/riscv/rvv/autovec/vls/perm-6.c | 6 + .../gcc.target/riscv/rvv/autovec/vls/perm-7.c | 6 + 32 files changed, 607 insertions(+), 176 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index d208b418e5f..6f48f7d6232 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -148,6 +148,14 @@ [(set_attr "type" "vmov") (set_attr "mode" "")]) +(define_insn "*mov_vls" + [(set (match_operand:VLSB 0 "register_operand" "=vr") + (match_operand:VLSB 1 "register_operand" " vr"))] + "TARGET_VECTOR" + "vmv1r.v\t%0,%1" + [(set_attr "type" "vmov") + (set_attr "mode" "")]) + (define_expand "movmisalign" [(set (match_operand:VLS 0 "nonimmediate_operand") (match_operand:VLS 1 "general_operand"))] diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 98cd0c07625..50ed1a90077 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -354,9 +354,9 @@ ;; ------------------------------------------------------------------------- (define_expand "vec_perm" - [(match_operand:V 0 "register_operand") - (match_operand:V 1 "register_operand") - (match_operand:V 2 "register_operand") + [(match_operand:V_VLS 0 "register_operand") + (match_operand:V_VLS 1 "register_operand") + (match_operand:V_VLS 2 "register_operand") (match_operand: 3 "vector_perm_operand")] "TARGET_VECTOR && GET_MODE_NUNITS (mode).is_constant ()" { diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 6dbf6b9f943..46d77ef927c 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -500,6 +500,8 @@ opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode, unsigned int autovectorize_vector_modes (vec *, bool); hash_set get_all_predecessors (basic_block); hash_set get_all_successors (basic_block); +bool cmp_lmul_le_one (machine_mode); +bool cmp_lmul_gt_one (machine_mode); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 1ca3f1dc8df..dc8c10f6ed2 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3435,4 +3435,26 @@ get_all_successors (basic_block bb) return blocks; } +/* Return true if the LMUL of comparison less than or equal to one. */ +bool +cmp_lmul_le_one (machine_mode mode) +{ + if (riscv_v_ext_vector_mode_p (mode)) + return known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR); + else if (riscv_v_ext_vls_mode_p (mode)) + return known_le (GET_MODE_BITSIZE (mode), TARGET_MIN_VLEN); + return false; +} + +/* Return true if the LMUL of comparison greater than one. */ +bool +cmp_lmul_gt_one (machine_mode mode) +{ + if (riscv_v_ext_vector_mode_p (mode)) + return known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR); + else if (riscv_v_ext_vls_mode_p (mode)) + return known_gt (GET_MODE_BITSIZE (mode), TARGET_MIN_VLEN); + return false; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 81682d95ba4..720fa474669 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5387,7 +5387,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) 1. If the operand is VECTOR REG, we print 'v'(vnsrl.wv). 2. If the operand is CONST_INT/CONST_VECTOR, we print 'i'(vnsrl.wi). 3. If the operand is SCALAR REG, we print 'x'(vnsrl.wx). */ - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) { if (REG_P (op)) asm_fprintf (file, "v"); @@ -9473,7 +9473,7 @@ riscv_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, rtx target, rtx op0, rtx op1, const vec_perm_indices &sel) { - if (TARGET_VECTOR && riscv_v_ext_vector_mode_p (vmode)) + if (TARGET_VECTOR && riscv_v_ext_mode_p (vmode)) return riscv_vector::expand_vec_perm_const (vmode, op_mode, target, op0, op1, sel); diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a98ed9fcbb6..2f7f7cbe08c 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -376,6 +376,85 @@ (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + + (V1QI "TARGET_VECTOR_VLS") + (V2QI "TARGET_VECTOR_VLS") + (V4QI "TARGET_VECTOR_VLS") + (V8QI "TARGET_VECTOR_VLS") + (V16QI "TARGET_VECTOR_VLS") + (V32QI "TARGET_VECTOR_VLS") + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V1HI "TARGET_VECTOR_VLS") + (V2HI "TARGET_VECTOR_VLS") + (V4HI "TARGET_VECTOR_VLS") + (V8HI "TARGET_VECTOR_VLS") + (V16HI "TARGET_VECTOR_VLS") + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1SI "TARGET_VECTOR_VLS") + (V2SI "TARGET_VECTOR_VLS") + (V4SI "TARGET_VECTOR_VLS") + (V8SI "TARGET_VECTOR_VLS") + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") + (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") + (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") + (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64") + (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") + (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256") + (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") + (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") + (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") + (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") + (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256") + (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512") + (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") + (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") + (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") ]) (define_mode_iterator VI [ @@ -646,6 +725,7 @@ (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") + (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64") @@ -1200,6 +1280,86 @@ (RVVM8DI "RVVM8DI") (RVVM4DI "RVVM4DI") (RVVM2DI "RVVM2DI") (RVVM1DI "RVVM1DI") (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI") + + (V1QI "V1QI") + (V2QI "V2QI") + (V4QI "V4QI") + (V8QI "V8QI") + (V16QI "V16QI") + (V32QI "V32QI") + (V64QI "V64QI") + (V128QI "V128QI") + (V256QI "V256QI") + (V512QI "V512QI") + (V1024QI "V1024QI") + (V2048QI "V2048QI") + (V4096QI "V4096QI") + (V1HI "V1HI") + (V2HI "V2HI") + (V4HI "V4HI") + (V8HI "V8HI") + (V16HI "V16HI") + (V32HI "V32HI") + (V64HI "V64HI") + (V128HI "V128HI") + (V256HI "V256HI") + (V512HI "V512HI") + (V1024HI "V1024HI") + (V2048HI "V2048HI") + (V1SI "V1SI") + (V2SI "V2SI") + (V4SI "V4SI") + (V8SI "V8SI") + (V16SI "V16SI") + (V32SI "V32SI") + (V64SI "V64SI") + (V128SI "V128SI") + (V256SI "V256SI") + (V512SI "V512SI") + (V1024SI "V1024SI") + (V1DI "V1DI") + (V2DI "V2DI") + (V4DI "V4DI") + (V8DI "V8DI") + (V16DI "V16DI") + (V32DI "V32DI") + (V64DI "V64DI") + (V128DI "V128DI") + (V256DI "V256DI") + (V512DI "V512DI") + (V1HF "V1HI") + (V2HF "V2HI") + (V4HF "V4HI") + (V8HF "V8HI") + (V16HF "V16HI") + (V32HF "V32HI") + (V64HF "V64HI") + (V128HF "V128HI") + (V256HF "V256HI") + (V512HF "V512HI") + (V1024HF "V1024HI") + (V2048HF "V2048HI") + (V1SF "V1SI") + (V2SF "V2SI") + (V4SF "V4SI") + (V8SF "V8SI") + (V16SF "V16SI") + (V32SF "V32SI") + (V64SF "V64SI") + (V128SF "V128SI") + (V256SF "V256SI") + (V512SF "V512SI") + (V1024SF "V1024SI") + (V1DF "V1DI") + (V2DF "V2DI") + (V4DF "V4DI") + (V8DF "V8DI") + (V16DF "V16DI") + (V32DF "V32DI") + (V64DF "V64DI") + (V128DF "V128DI") + (V256DF "V256DI") + (V512DF "V512DI") ]) (define_mode_attr VINDEXEI16 [ @@ -1216,6 +1376,85 @@ (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI") (RVVM8DF "RVVM2HI") (RVVM4DF "RVVM1HI") (RVVM2DF "RVVMF2HI") (RVVM1DF "RVVMF4HI") + + (V1QI "V1HI") + (V2QI "V2HI") + (V4QI "V4HI") + (V8QI "V8HI") + (V16QI "V16HI") + (V32QI "V32HI") + (V64QI "V64HI") + (V128QI "V128HI") + (V256QI "V256HI") + (V512QI "V512HI") + (V1024QI "V1024HI") + (V2048QI "V2048HI") + (V1HI "V1HI") + (V2HI "V2HI") + (V4HI "V4HI") + (V8HI "V8HI") + (V16HI "V16HI") + (V32HI "V32HI") + (V64HI "V64HI") + (V128HI "V128HI") + (V256HI "V256HI") + (V512HI "V512HI") + (V1024HI "V1024HI") + (V2048HI "V2048HI") + (V1SI "V1HI") + (V2SI "V2HI") + (V4SI "V4HI") + (V8SI "V8HI") + (V16SI "V16HI") + (V32SI "V32HI") + (V64SI "V64HI") + (V128SI "V128HI") + (V256SI "V256HI") + (V512SI "V512HI") + (V1024SI "V1024HI") + (V1DI "V1HI") + (V2DI "V2HI") + (V4DI "V4HI") + (V8DI "V8HI") + (V16DI "V16HI") + (V32DI "V32HI") + (V64DI "V64HI") + (V128DI "V128HI") + (V256DI "V256HI") + (V512DI "V512HI") + (V1HF "V1HI") + (V2HF "V2HI") + (V4HF "V4HI") + (V8HF "V8HI") + (V16HF "V16HF") + (V32HF "V32HI") + (V64HF "V64HI") + (V128HF "V128HI") + (V256HF "V256HI") + (V512HF "V512HI") + (V1024HF "V1024HI") + (V2048HF "V2048HI") + (V1SF "V1HI") + (V2SF "V2HI") + (V4SF "V4HI") + (V8SF "V8HI") + (V16SF "V16HI") + (V32SF "V32HI") + (V64SF "V64HI") + (V128SF "V128HI") + (V256SF "V256HI") + (V512SF "V512HI") + (V1024SF "V1024HI") + (V1DF "V1HI") + (V2DF "V2HI") + (V4DF "V4HI") + (V8DF "V8HI") + (V16DF "V16HI") + (V32DF "V32HI") + (V64DF "V64HI") + (V128DF "V128HI") + (V256DF "V256HI") + (V512DF "V512HI") ]) (define_mode_attr VM [ @@ -1587,11 +1826,11 @@ (RVVM8DF "SF") (RVVM4DF "SF") (RVVM2DF "SF") (RVVM1DF "SF") ;; VLS modes. - (V2HI "QI") (V4HI "QI") (V8HI "QI") (V16HI "QI") (V32HI "QI") (V64HI "QI") (V128HI "QI") (V256HI "QI") + (V1HI "QI") (V2HI "QI") (V4HI "QI") (V8HI "QI") (V16HI "QI") (V32HI "QI") (V64HI "QI") (V128HI "QI") (V256HI "QI") (V512HI "QI") (V1024HI "QI") (V2048HI "QI") - (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "HI") (V128SI "HI") (V256SI "HI") + (V1SI "HI") (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "HI") (V128SI "HI") (V256SI "HI") (V512SI "HI") (V1024SI "HI") - (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "SI") (V128DI "SI") (V256DI "SI") (V512DI "SI") + (V1DI "SI") (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "SI") (V128DI "SI") (V256DI "SI") (V512DI "SI") ]) (define_mode_attr nf [ @@ -1945,10 +2184,30 @@ (define_mode_attr VDEMOTE [ (RVVM8DI "RVVM8SI") (RVVM4DI "RVVM4SI") (RVVM2DI "RVVM2SI") (RVVM1DI "RVVM1SI") + (V1DI "V1SI") + (V2DI "V2SI") + (V4DI "V4SI") + (V8DI "V8SI") + (V16DI "V16SI") + (V32DI "V32SI") + (V64DI "V64SI") + (V128DI "V128SI") + (V256DI "V256SI") + (V512DI "V512SI") ]) (define_mode_attr VMDEMOTE [ (RVVM8DI "RVVMF4BI") (RVVM4DI "RVVMF8BI") (RVVM2DI "RVVMF16BI") (RVVM1DI "RVVMF32BI") + (V1DI "V1BI") + (V2DI "V2BI") + (V4DI "V4BI") + (V8DI "V8BI") + (V16DI "V16BI") + (V32DI "V32BI") + (V64DI "V64BI") + (V128DI "V128BI") + (V256DI "V256BI") + (V512DI "V512BI") ]) (define_mode_attr gs_extension [ @@ -2425,6 +2684,21 @@ (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")]) +(define_mode_iterator VLSB [ + (V1BI "TARGET_VECTOR_VLS") + (V2BI "TARGET_VECTOR_VLS") + (V4BI "TARGET_VECTOR_VLS") + (V8BI "TARGET_VECTOR_VLS") + (V16BI "TARGET_VECTOR_VLS") + (V32BI "TARGET_VECTOR_VLS") + (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")]) + ;; VLS modes that has NUNITS < 32. (define_mode_iterator VLS_AVL_IMM [ (V1QI "TARGET_VECTOR_VLS") @@ -2574,18 +2848,18 @@ (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")]) (define_mode_iterator VLSF [ - (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") - (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") - (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256") - (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512") - (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") - (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") - (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") + (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") + (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") + (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") + (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") + (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048") + (V2048HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096") (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 7c086d40f7d..58e659e5cd4 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1588,19 +1588,19 @@ (set_attr "vl_op_idx" "3")]) (define_insn "@pred_merge" - [(set (match_operand:V 0 "register_operand" "=vd,vd,vd,vd") - (if_then_else:V + [(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd") + (if_then_else:V_VLS (unspec: [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (vec_merge:V - (match_operand:V 3 "vector_arith_operand" " vr,vr,vi,vi") - (match_operand:V 2 "register_operand" " vr,vr,vr,vr") + (vec_merge:V_VLS + (match_operand:V_VLS 3 "vector_arith_operand" " vr,vr,vi,vi") + (match_operand:V_VLS 2 "register_operand" " vr,vr,vr,vr") (match_operand: 4 "register_operand" " vm,vm,vm,vm")) - (match_operand:V 1 "vector_merge_operand" " vu, 0,vu, 0")))] + (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0,vu, 0")))] "TARGET_VECTOR" "vmerge.v%o3m\t%0,%2,%v3,%4" [(set_attr "type" "vimerge") @@ -4204,8 +4204,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_ltge_operator" - [(match_operand:VI 4 "register_operand") - (match_operand:VI 5 "vector_arith_operand")]) + [(match_operand:V_VLSI 4 "register_operand") + (match_operand:V_VLSI 5 "vector_arith_operand")]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" {}) @@ -4221,8 +4221,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "comparison_except_ltge_operator" - [(match_operand:VI 3 "register_operand" " vr") - (match_operand:VI 4 "vector_arith_operand" "vrvi")]) + [(match_operand:V_VLSI 3 "register_operand" " vr") + (match_operand:V_VLSI 4 "vector_arith_operand" "vrvi")]) (match_dup 1)))] "TARGET_VECTOR" "vms%B2.v%o4\t%0,%3,%v4,v0.t" @@ -4245,10 +4245,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_ltge_operator" - [(match_operand:VI 4 "register_operand" " vr, vr, vr, vr") - (match_operand:VI 5 "vector_arith_operand" " vr, vr, vi, vi")]) + [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi")]) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4265,10 +4265,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_ltge_operator" - [(match_operand:VI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr") - (match_operand:VI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")]) + [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr") + (match_operand:V_VLSI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")]) (match_operand: 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4284,8 +4284,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "ltge_operator" - [(match_operand:VI 4 "register_operand") - (match_operand:VI 5 "vector_neg_arith_operand")]) + [(match_operand:V_VLSI 4 "register_operand") + (match_operand:V_VLSI 5 "vector_neg_arith_operand")]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" {}) @@ -4301,8 +4301,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "ltge_operator" - [(match_operand:VI 3 "register_operand" " vr") - (match_operand:VI 4 "vector_neg_arith_operand" "vrvj")]) + [(match_operand:V_VLSI 3 "register_operand" " vr") + (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")]) (match_dup 1)))] "TARGET_VECTOR" "vms%B2.v%o4\t%0,%3,%v4,v0.t" @@ -4325,10 +4325,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "ltge_operator" - [(match_operand:VI 4 "register_operand" " vr, vr, vr, vr") - (match_operand:VI 5 "vector_neg_arith_operand" " vr, vr, vj, vj")]) + [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj")]) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4345,10 +4345,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "ltge_operator" - [(match_operand:VI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr") - (match_operand:VI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")]) + [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr") + (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")]) (match_operand: 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4364,8 +4364,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_QHS 4 "register_operand") - (vec_duplicate:VI_QHS + [(match_operand:V_VLSI_QHS 4 "register_operand") + (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand"))]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" @@ -4382,8 +4382,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "comparison_except_eqge_operator" - [(match_operand:VI_QHS 3 "register_operand" " vr") - (vec_duplicate:VI_QHS + [(match_operand:V_VLSI_QHS 3 "register_operand" " vr") + (vec_duplicate:V_VLSI_QHS (match_operand: 4 "register_operand" " r"))]) (match_dup 1)))] "TARGET_VECTOR" @@ -4407,11 +4407,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_QHS 4 "register_operand" " vr, vr") - (vec_duplicate:VI_QHS + [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr") + (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r"))]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4428,11 +4428,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_QHS 4 "register_operand" " vr, 0, 0, vr, vr") - (vec_duplicate:VI_QHS + [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr") + (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r, r"))]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4448,9 +4448,9 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_QHS + [(vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand")) - (match_operand:VI_QHS 4 "register_operand")]) + (match_operand:V_VLSI_QHS 4 "register_operand")]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" {}) @@ -4466,9 +4466,9 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "equality_operator" - [(vec_duplicate:VI_QHS + [(vec_duplicate:V_VLSI_QHS (match_operand: 4 "register_operand" " r")) - (match_operand:VI_QHS 3 "register_operand" " vr")]) + (match_operand:V_VLSI_QHS 3 "register_operand" " vr")]) (match_dup 1)))] "TARGET_VECTOR" "vms%B2.vx\t%0,%3,%4,v0.t" @@ -4491,11 +4491,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_QHS + [(vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r")) - (match_operand:VI_QHS 4 "register_operand" " vr, vr")]) + (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4512,11 +4512,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_QHS + [(vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:VI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")]) + (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4534,8 +4534,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_D 4 "register_operand") - (vec_duplicate:VI_D + [(match_operand:V_VLSI_D 4 "register_operand") + (vec_duplicate:V_VLSI_D (match_operand: 5 "reg_or_int_operand"))]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" @@ -4573,9 +4573,9 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_D + [(vec_duplicate:V_VLSI_D (match_operand: 5 "reg_or_int_operand")) - (match_operand:VI_D 4 "register_operand")]) + (match_operand:V_VLSI_D 4 "register_operand")]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" { @@ -4605,8 +4605,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "comparison_except_eqge_operator" - [(match_operand:VI_D 3 "register_operand" " vr") - (vec_duplicate:VI_D + [(match_operand:V_VLSI_D 3 "register_operand" " vr") + (vec_duplicate:V_VLSI_D (match_operand: 4 "register_operand" " r"))]) (match_dup 1)))] "TARGET_VECTOR" @@ -4629,9 +4629,9 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "equality_operator" - [(vec_duplicate:VI_D + [(vec_duplicate:V_VLSI_D (match_operand: 4 "register_operand" " r")) - (match_operand:VI_D 3 "register_operand" " vr")]) + (match_operand:V_VLSI_D 3 "register_operand" " vr")]) (match_dup 1)))] "TARGET_VECTOR" "vms%B2.vx\t%0,%3,%4,v0.t" @@ -4654,11 +4654,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_D 4 "register_operand" " vr, vr") - (vec_duplicate:VI_D + [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr") + (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r"))]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4675,11 +4675,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_D 4 "register_operand" " vr, 0, 0, vr, vr") - (vec_duplicate:VI_D + [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") + (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r, r"))]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4696,11 +4696,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_D + [(vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r")) - (match_operand:VI_D 4 "register_operand" " vr, vr")]) + (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4717,11 +4717,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_D + [(vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:VI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) + (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4737,8 +4737,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "comparison_except_eqge_operator" - [(match_operand:VI_D 3 "register_operand" " vr") - (vec_duplicate:VI_D + [(match_operand:V_VLSI_D 3 "register_operand" " vr") + (vec_duplicate:V_VLSI_D (sign_extend: (match_operand: 4 "register_operand" " r")))]) (match_dup 1)))] @@ -4763,12 +4763,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_D 4 "register_operand" " vr, vr") - (vec_duplicate:VI_D + [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr") + (vec_duplicate:V_VLSI_D (sign_extend: (match_operand: 5 "register_operand" " r, r")))]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4784,12 +4784,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:VI_D 4 "register_operand" " vr, 0, 0, vr, vr") - (vec_duplicate:VI_D + [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") + (vec_duplicate:V_VLSI_D (sign_extend: (match_operand: 5 "register_operand" " r, r, r, r, r")))]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4805,10 +4805,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 2 "equality_operator" - [(vec_duplicate:VI_D + [(vec_duplicate:V_VLSI_D (sign_extend: (match_operand: 4 "register_operand" " r"))) - (match_operand:VI_D 3 "register_operand" " vr")]) + (match_operand:V_VLSI_D 3 "register_operand" " vr")]) (match_dup 1)))] "TARGET_VECTOR" "vms%B2.vx\t%0,%3,%4,v0.t" @@ -4831,12 +4831,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_D + [(vec_duplicate:V_VLSI_D (sign_extend: (match_operand: 5 "register_operand" " r, r"))) - (match_operand:VI_D 4 "register_operand" " vr, vr")]) + (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4852,12 +4852,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" - [(vec_duplicate:VI_D + [(vec_duplicate:V_VLSI_D (sign_extend: (match_operand: 5 "register_operand" " r, r, r, r, r"))) - (match_operand:VI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) + (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)" + "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") (set_attr "mode" "")]) @@ -4886,8 +4886,8 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "ge_operator" - [(match_operand:VI 4 "register_operand") - (vec_duplicate:VI + [(match_operand:V_VLSI 4 "register_operand") + (vec_duplicate:V_VLSI (match_operand: 5 "reg_or_int_operand"))]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" @@ -5848,18 +5848,18 @@ ;; For example, if we have vmxor.mm v1,v1,v1. It will be optmized as vmclr.m which ;; is generated by pred_mov. (define_insn "@pred_" - [(set (match_operand:VB 0 "register_operand" "=vr") - (if_then_else:VB - (unspec:VB - [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (if_then_else:VB_VLS + (unspec:VB_VLS + [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 5 "vector_length_operand" " rK") (match_operand 6 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_bitwise:VB - (match_operand:VB 3 "register_operand" " vr") - (match_operand:VB 4 "register_operand" " vr")) - (match_operand:VB 2 "vector_undef_operand" " vu")))] + (any_bitwise:VB_VLS + (match_operand:VB_VLS 3 "register_operand" " vr") + (match_operand:VB_VLS 4 "register_operand" " vr")) + (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))] "TARGET_VECTOR" "vm.mm\t%0,%3,%4" [(set_attr "type" "vmalu") @@ -5868,19 +5868,19 @@ (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))]) (define_insn "@pred_n" - [(set (match_operand:VB 0 "register_operand" "=vr") - (if_then_else:VB - (unspec:VB - [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (if_then_else:VB_VLS + (unspec:VB_VLS + [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 5 "vector_length_operand" " rK") (match_operand 6 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (not:VB - (any_bitwise:VB - (match_operand:VB 3 "register_operand" " vr") - (match_operand:VB 4 "register_operand" " vr"))) - (match_operand:VB 2 "vector_undef_operand" " vu")))] + (not:VB_VLS + (any_bitwise:VB_VLS + (match_operand:VB_VLS 3 "register_operand" " vr") + (match_operand:VB_VLS 4 "register_operand" " vr"))) + (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))] "TARGET_VECTOR" "vm.mm\t%0,%3,%4" [(set_attr "type" "vmalu") @@ -5889,19 +5889,19 @@ (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))]) (define_insn "@pred_not" - [(set (match_operand:VB 0 "register_operand" "=vr") - (if_then_else:VB - (unspec:VB - [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (if_then_else:VB_VLS + (unspec:VB_VLS + [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 5 "vector_length_operand" " rK") (match_operand 6 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (and_ior:VB - (match_operand:VB 3 "register_operand" " vr") - (not:VB - (match_operand:VB 4 "register_operand" " vr"))) - (match_operand:VB 2 "vector_undef_operand" " vu")))] + (and_ior:VB_VLS + (match_operand:VB_VLS 3 "register_operand" " vr") + (not:VB_VLS + (match_operand:VB_VLS 4 "register_operand" " vr"))) + (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))] "TARGET_VECTOR" "vmn.mm\t%0,%3,%4" [(set_attr "type" "vmalu") @@ -5910,17 +5910,17 @@ (set (attr "avl_type") (symbol_ref "INTVAL (operands[6])"))]) (define_insn "@pred_not" - [(set (match_operand:VB 0 "register_operand" "=vr") - (if_then_else:VB - (unspec:VB - [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (if_then_else:VB_VLS + (unspec:VB_VLS + [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 4 "vector_length_operand" " rK") (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (not:VB - (match_operand:VB 3 "register_operand" " vr")) - (match_operand:VB 2 "vector_undef_operand" " vu")))] + (not:VB_VLS + (match_operand:VB_VLS 3 "register_operand" " vr")) + (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))] "TARGET_VECTOR" "vmnot.m\t%0,%3" [(set_attr "type" "vmalu") @@ -8186,8 +8186,8 @@ ;; vslide instructions (define_insn "@pred_slide" - [(set (match_operand:V 0 "register_operand" "") - (unspec:V + [(set (match_operand:V_VLS 0 "register_operand" "") + (unspec:V_VLS [(unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -8196,8 +8196,8 @@ (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0") - (match_operand:V 3 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:V_VLS 3 "register_operand" " vr, vr, vr, vr") (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))] "TARGET_VECTOR" "vslide.v%o4\t%0,%3,%4%p1" @@ -8206,8 +8206,8 @@ ;; vslide1 instructions (define_insn "@pred_slide" - [(set (match_operand:VI_QHS 0 "register_operand" "") - (unspec:VI_QHS + [(set (match_operand:V_VLSI_QHS 0 "register_operand" "") + (unspec:V_VLSI_QHS [(unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -8216,8 +8216,8 @@ (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0") - (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:V_VLSI_QHS 3 "register_operand" " vr, vr, vr, vr") (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))] "TARGET_VECTOR" "vslide.vx\t%0,%3,%z4%p1" @@ -8225,8 +8225,8 @@ (set_attr "mode" "")]) (define_expand "@pred_slide" - [(set (match_operand:VI_D 0 "register_operand") - (unspec:VI_D + [(set (match_operand:V_VLSI_D 0 "register_operand") + (unspec:V_VLSI_D [(unspec: [(match_operand: 1 "vector_mask_operand") (match_operand 5 "reg_or_int_operand") @@ -8235,8 +8235,8 @@ (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_D 2 "vector_merge_operand") - (match_operand:VI_D 3 "register_operand") + (match_operand:V_VLSI_D 2 "vector_merge_operand") + (match_operand:V_VLSI_D 3 "register_operand") (match_operand: 4 "reg_or_int_operand")] VSLIDES1))] "TARGET_VECTOR" { @@ -8247,8 +8247,8 @@ }) (define_insn "*pred_slide" - [(set (match_operand:VI_D 0 "register_operand" "") - (unspec:VI_D + [(set (match_operand:V_VLSI_D 0 "register_operand" "") + (unspec:V_VLSI_D [(unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -8257,8 +8257,8 @@ (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0") - (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr") (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))] "TARGET_VECTOR" "vslide.vx\t%0,%3,%z4%p1" @@ -8266,8 +8266,8 @@ (set_attr "mode" "")]) (define_insn "*pred_slide_extended" - [(set (match_operand:VI_D 0 "register_operand" "") - (unspec:VI_D + [(set (match_operand:V_VLSI_D 0 "register_operand" "") + (unspec:V_VLSI_D [(unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -8276,8 +8276,8 @@ (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0") - (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0") + (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr") (sign_extend: (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))] "TARGET_VECTOR" @@ -8307,8 +8307,8 @@ ;; vrgather (define_insn "@pred_gather" - [(set (match_operand:V 0 "register_operand" "=&vr, &vr") - (if_then_else:V + [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr") + (if_then_else:V_VLS (unspec: [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") @@ -8317,18 +8317,18 @@ (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (unspec:V - [(match_operand:V 3 "register_operand" " vr, vr") + (unspec:V_VLS + [(match_operand:V_VLS 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER) - (match_operand:V 2 "vector_merge_operand" " vu, 0")))] + (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vrgather.vv\t%0,%3,%4%p1" [(set_attr "type" "vgather") (set_attr "mode" "")]) (define_insn "@pred_gather_scalar" - [(set (match_operand:V 0 "register_operand" "=&vr, &vr") - (if_then_else:V + [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr") + (if_then_else:V_VLS (unspec: [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") @@ -8337,10 +8337,10 @@ (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (unspec:V - [(match_operand:V 3 "register_operand" " vr, vr") + (unspec:V_VLS + [(match_operand:V_VLS 3 "register_operand" " vr, vr") (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER) - (match_operand:V 2 "vector_merge_operand" " vu, 0")))] + (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vrgather.v%o4\t%0,%3,%4%p1" [(set_attr "type" "vgather") @@ -8369,8 +8369,8 @@ ;; vcompress (define_insn "@pred_compress" - [(set (match_operand:V 0 "register_operand" "=&vr, &vr") - (unspec:V + [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr") + (unspec:V_VLS [(unspec: [(match_operand: 3 "register_operand" " vm, vm") (match_operand 4 "vector_length_operand" " rK, rK") @@ -8378,8 +8378,8 @@ (match_operand 6 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:V 2 "register_operand" " vr, vr") - (match_operand:V 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))] + (match_operand:V_VLS 2 "register_operand" " vr, vr") + (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))] "TARGET_VECTOR" "vcompress.vm\t%0,%2,%3" [(set_attr "type" "vcompress") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c index 3571a325f73..34622ce9aff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c @@ -21,6 +21,6 @@ f (int8_t *restrict a, int8_t *restrict b, int n) /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ /* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ /* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c index 8c5c65152c8..80c77ef679a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c @@ -21,6 +21,6 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n) /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ /* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ /* { dg-final { scan-assembler-not {\tvmul} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c index 67dbadafc48..50d06d501ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c index fde54e1f059..75298bd7525 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c @@ -21,4 +21,4 @@ f (int8_t *restrict a, int8_t *restrict b, int n) /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c index 600699be9d1..c1b31a430f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c @@ -21,4 +21,4 @@ f (int8_t *restrict a, int8_t *restrict b, int n) /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c new file mode 100644 index 00000000000..537a032947e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/compress-1.c" + +/* { dg-final { scan-assembler-times {\tvcompress\.vm} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c new file mode 100644 index 00000000000..e643147105f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/compress-2.c" + +/* { dg-final { scan-assembler-times {\tvcompress\.vm} 5 } } */ +/* { dg-final { scan-assembler-times {\tvslideup} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c new file mode 100644 index 00000000000..5e872942c9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/compress-3.c" + +/* { dg-final { scan-assembler-times {\tvcompress.vm} 8 } } */ +/* { dg-final { scan-assembler-times {\tvslideup} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c new file mode 100644 index 00000000000..a4ceb62912a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/compress-4.c" + +/* { dg-final { scan-assembler-times {\tvcompress.vm} 11 } } */ +/* { dg-final { scan-assembler-times {\tvslideup} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c new file mode 100644 index 00000000000..f407027ae40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/compress-5.c" + +/* { dg-final { scan-assembler-times {\tvcompress.vm} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c new file mode 100644 index 00000000000..ffc0b8fa5b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/compress-6.c" + +/* { dg-final { scan-assembler-times {\tvcompress.vm} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c new file mode 100644 index 00000000000..9cbc845b38b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/merge-1.c" + +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c new file mode 100644 index 00000000000..e270db947df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/merge-2.c" + +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c new file mode 100644 index 00000000000..033952ffbe4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/merge-3.c" + +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c new file mode 100644 index 00000000000..62ed1a5fd17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/merge-4.c" + +/* dg-final scan-assembler-times {\tvmerge.vvm} 11 */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c new file mode 100644 index 00000000000..42fa2ec7682 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/merge-5.c" + +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c new file mode 100644 index 00000000000..d5222f6cb28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/merge-6.c" + +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 5 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c new file mode 100644 index 00000000000..bd097f033dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/merge-7.c" + +/* { dg-final { scan-assembler-times {\tvmerge.vvm} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c new file mode 100644 index 00000000000..327913ba5e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/perm-1.c" + +/* { dg-final { scan-assembler-times {vrgather\.vi\tv[0-9]+,\s*v[0-9]+,\s*1} 31 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c new file mode 100644 index 00000000000..d56231268fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/perm-2.c" + +/* { dg-final { scan-assembler-times {vrgather\.vi\tv[0-9]+,\s*v[0-9]+,\s*31} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c new file mode 100644 index 00000000000..87319e373da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/perm-3.c" + +/* { dg-final { scan-assembler-times {vrgather\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c new file mode 100644 index 00000000000..46cad8ea2f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/perm-4.c" + +/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */ +/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */ +/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c new file mode 100644 index 00000000000..3460315bac3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/perm-5.c" + +/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c new file mode 100644 index 00000000000..a2a722f4897 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/perm-6.c" + +/* { dg-final { scan-assembler-times {vrgather\.vi\tv[0-9]+,\s*v[0-9]+,\s*1} 31 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c new file mode 100644 index 00000000000..b474ccfd7ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include "../vls-vlmax/perm-7.c" + +/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 31 } } */