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Fri, 08 Sep 2023 11:17:08 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 1/5] RISC-V: Update Types for Vector Instructions Date: Fri, 8 Sep 2023 11:16:45 -0700 Message-ID: <20230908181659.3345602-2-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230908181659.3345602-1-ewlu@rivosinc.com> References: <20230908181659.3345602-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776494463955722490 X-GMAIL-MSGID: 1776494463955722490 This patch adds types to vector instructions that were added after or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html gcc/ChangeLog: * config/riscv/autovec-opt.md: Update types * config/riscv/autovec.md: likewise Signed-off-by: Edwin Lu --- Changes in V2: - Add types to insns missed by prev version --- gcc/config/riscv/autovec-opt.md | 72 ++++++++++++++++++++++----------- gcc/config/riscv/autovec.md | 52 ++++++++++++++++-------- 2 files changed, 83 insertions(+), 41 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 3aaee54f02a..58e80044f1e 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -628,7 +628,8 @@ (define_insn_and_split "*cond_abs" gen_int_mode (GET_MODE_NUNITS (mode), Pmode), const0_rtx)); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine vfsqrt.v and cond_mask (define_insn_and_split "*cond_" @@ -666,7 +667,8 @@ (define_insn_and_split "*copysign_neg" riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode), riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf2) and vcond_mask (define_insn_and_split "*cond_" @@ -685,7 +687,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf4) and vcond_mask (define_insn_and_split "*cond_" @@ -704,7 +707,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf8) and vcond_mask (define_insn_and_split "*cond_" @@ -723,7 +727,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" @@ -743,7 +748,8 @@ (define_insn_and_split "*cond_trunc" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine FP extend(vf2) and vcond_mask (define_insn_and_split "*cond_extend" @@ -762,7 +768,8 @@ (define_insn_and_split "*cond_extend" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine FP trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" @@ -782,7 +789,8 @@ (define_insn_and_split "*cond_trunc" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(FP->INT) + vcond_mask (define_insn_and_split "*cond_" @@ -802,7 +810,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(INT->FP) + vcond_mask (define_insn_and_split "*cond_" @@ -822,7 +831,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(FP->2xINT) + vcond_mask (define_insn_and_split "*cond_" @@ -842,7 +852,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(INT->2xFP) + vcond_mask (define_insn_and_split "*cond_" @@ -862,7 +873,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(2xFP->INT) + vcond_mask (define_insn_and_split "*cond_" @@ -882,7 +894,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(2xINT->FP) + vcond_mask (define_insn_and_split "*cond_2" @@ -902,7 +915,8 @@ (define_insn_and_split "*cond_2" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; ============================================================================= ;; Combine extend + binop to widen_binop @@ -925,7 +939,8 @@ (define_insn_and_split "*dual_widen_ mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) (define_insn_and_split "*single_widen_sub" [(set (match_operand:VWEXTI 0 "register_operand") @@ -942,7 +957,8 @@ (define_insn_and_split "*single_widen_sub" mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "viwalu")]) (define_insn_and_split "*single_widen_add" [(set (match_operand:VWEXTI 0 "register_operand") @@ -959,7 +975,8 @@ (define_insn_and_split "*single_widen_add" mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "viwalu")]) ;; This combine pattern does not correspond to an single instruction, ;; i.e. there is no vwmul.wv instruction. This is a temporary pattern @@ -985,7 +1002,8 @@ (define_insn_and_split "*single_widen_mult" insn_code icode = code_for_pred (MULT, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, ops); DONE; -}) +} +[(set_attr "type" "viwmul")]) (define_insn_and_split "*dual_widen_mulsu" [(set (match_operand:VWEXTI 0 "register_operand") @@ -1002,7 +1020,8 @@ (define_insn_and_split "*dual_widen_mulsu" insn_code icode = code_for_pred_widen_mulsu (mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) (define_insn_and_split "*dual_widen_mulus" [(set (match_operand:VWEXTI 0 "register_operand") @@ -1019,7 +1038,8 @@ (define_insn_and_split "*dual_widen_mulus" insn_code icode = code_for_pred_widen_mulsu (mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) (define_insn_and_split "*dual_widen_" [(set (match_operand:VWEXTF 0 "register_operand") @@ -1036,7 +1056,8 @@ (define_insn_and_split "*dual_widen_" insn_code icode = code_for_pred_dual_widen (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vector")]) (define_insn_and_split "*single_widen_add" [(set (match_operand:VWEXTF 0 "register_operand") @@ -1052,7 +1073,8 @@ (define_insn_and_split "*single_widen_add" insn_code icode = code_for_pred_single_widen_add (mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfwalu")]) (define_insn_and_split "*single_widen_sub" [(set (match_operand:VWEXTF 0 "register_operand") @@ -1068,7 +1090,8 @@ (define_insn_and_split "*single_widen_sub" insn_code icode = code_for_pred_single_widen_sub (mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfwalu")]) ;; This combine pattern does not correspond to an single instruction, ;; i.e. there is no vfwmul.wv instruction. This is a temporary pattern @@ -1094,4 +1117,5 @@ (define_insn_and_split "*single_widen_mult" riscv_vector::emit_vlmax_insn (code_for_pred (MULT, mode), riscv_vector::BINARY_OP_FRM_DYN, ops); DONE; -}) +} +[(set_attr "type" "vfwmul")]) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 98cd0c07625..ed4f0f8607a 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -432,7 +432,8 @@ (define_insn_and_split "3" riscv_vector::emit_vlmax_insn (code_for_pred (, mode), riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vialu")]) ;; ------------------------------------------------------------------------- ;; ---- [INT] Binary shifts by scalar. @@ -561,6 +562,7 @@ (define_insn_and_split "@vcond_mask_" riscv_vector::MERGE_OP, operands); DONE; } + [(set_attr "type" "vector")] ) ;; ------------------------------------------------------------------------- @@ -648,7 +650,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_vf4 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vext")]) (define_insn_and_split "2" [(set (match_operand:VOEXTI 0 "register_operand") @@ -662,7 +665,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_vf8 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vext")]) ;; ------------------------------------------------------------------------- ;; ---- [INT] Truncation @@ -818,7 +822,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfcvtftoi")]) ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] Conversions @@ -840,7 +845,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfcvtitof")]) ;; ========================================================================= ;; == Widening/narrowing Conversions @@ -865,7 +871,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_widen (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfwcvtftoi")]) ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] Widening Conversions @@ -886,7 +893,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_widen (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfwcvtitof")]) ;; ------------------------------------------------------------------------- ;; ---- [INT<-FP] Narrowing Conversions @@ -907,7 +915,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_narrow (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfncvtftoi")]) ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] Narrowing Conversions @@ -928,7 +937,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred_narrow (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfncvtitof")]) ;; ========================================================================= ;; == Unary arithmetic @@ -952,7 +962,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vialu")]) ;; ------------------------------------------------------------------------------- ;; - [INT] ABS expansion to vmslt and vneg. @@ -976,7 +987,8 @@ (define_insn_and_split "abs2" riscv_vector::emit_vlmax_insn (code_for_pred (NEG, mode), riscv_vector::UNARY_OP_TAMU, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; ------------------------------------------------------------------------------- ;; ---- [FP] Unary operations @@ -996,7 +1008,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) ;; ------------------------------------------------------------------------------- ;; - [FP] Square root @@ -1016,7 +1029,8 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfsqrt")]) ;; ========================================================================= ;; == Ternary arithmetic @@ -1480,7 +1494,8 @@ (define_insn_and_split "3" riscv_vector::emit_vlmax_insn (code_for_pred (, mode), riscv_vector::BINARY_OP_FRM_DYN, operands); DONE; -}) +} +[(set_attr "type" "vfalu")]) ;; ------------------------------------------------------------------------- ;; Includes: @@ -1500,7 +1515,8 @@ (define_insn_and_split "3" riscv_vector::emit_vlmax_insn (code_for_pred (, mode), riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vfminmax")]) ;; ------------------------------------------------------------------------------- ;; ---- [FP] Sign copying @@ -1566,7 +1582,8 @@ (define_insn_and_split "smul3_highpart" insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vimul")]) (define_insn_and_split "umul3_highpart" [(set (match_operand:VFULLI 0 "register_operand") @@ -1581,7 +1598,8 @@ (define_insn_and_split "umul3_highpart" insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vimul")]) ;; ------------------------------------------------------------------------- ;; ---- [INT] Conditional unary operations