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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x24-20020a170906299800b0099cadcf13cesm7764072eje.66.2023.09.05.08.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 08:42:37 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law Subject: [PATCH] riscv: xtheadbb: Enable constant synthesis with th.srri Date: Tue, 5 Sep 2023 17:42:34 +0200 Message-ID: <20230905154234.3316144-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776212864991138115 X-GMAIL-MSGID: 1776212864991138115 From: Christoph Müllner Some constants can be built up using rotate-right instructions. The code that enables this can be found in riscv_build_integer_1(). However, this functionality is only available for Zbb, which includes the rori instruction. This patch enables this also for XTheadBb, which includes the th.srri instruction. Signed-off-by: Christoph Müllner gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer_1): Enable constant synthesis with rotate-right for XTheadBb. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbb-li-rotr.c: New test. --- gcc/config/riscv/riscv.cc | 2 +- .../gcc.target/riscv/xtheadbb-li-rotr.c | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2db9c81ac8b..ef63079de8e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -566,7 +566,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], } } - if (cost > 2 && TARGET_64BIT && TARGET_ZBB) + if (cost > 2 && TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)) { int leading_ones = clz_hwi (~value); int trailing_ones = ctz_hwi (~value); diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c new file mode 100644 index 00000000000..ecd50448d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb" } */ + +long +li_rori (void) +{ + return 0xffff77ffffffffffL; +} + +long +li_rori_2 (void) +{ + return 0x77ffffffffffffffL; +} + +long +li_rori_3 (void) +{ + return 0xfffffffeefffffffL; +} + +long +li_rori_4 (void) +{ + return 0x5ffffffffffffff5L; +} + +long +li_rori_5 (void) +{ + return 0xaffffffffffffffaL; +} + +/* { dg-final { scan-assembler-times "th.srri\t" 5 } } */