diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 7ef29637e33..31b6c4ae714 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -255,6 +255,28 @@ (define_insn_and_split "<optab><mode>3"
 [(set_attr "type" "vector")]
 )
 
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfsgnj.vv
+;; - vfsgnj.vf
+;; -------------------------------------------------------------------------
+(define_insn_and_split "copysign<mode>3"
+  [(set (match_operand:VLSF 0 "register_operand")
+    (unspec:VLSF
+      [(match_operand:VLSF  1 "register_operand")
+       (match_operand:VLSF  2 "register_operand")] UNSPEC_VCOPYSIGN))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode),
+				   riscv_vector::BINARY_OP, operands);
+    DONE;
+  }
+  [(set_attr "type" "vector")]
+)
+
 ;; -------------------------------------------------------------------------------
 ;; ---- [INT] Unary operations
 ;; -------------------------------------------------------------------------------
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 9d7b4bbe1d4..fc985ff6a01 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6166,8 +6166,8 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
 	(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
 
 (define_insn "@pred_<copysign><mode>"
-  [(set (match_operand:VF 0 "register_operand"           "=vd, vd, vr, vr")
-	(if_then_else:VF
+  [(set (match_operand:V_VLSF 0 "register_operand"       "=vd, vd, vr, vr")
+	(if_then_else:V_VLSF
 	  (unspec:<VM>
 	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
 	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
@@ -6176,10 +6176,10 @@ (define_insn "@pred_<copysign><mode>"
 	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VF
-	    [(match_operand:VF 3 "register_operand"       " vr, vr, vr, vr")
-	     (match_operand:VF 4 "register_operand"       " vr, vr, vr, vr")] VCOPYSIGNS)
-	  (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
+	  (unspec:V_VLSF
+	    [(match_operand:V_VLSF 3 "register_operand"  " vr, vr, vr, vr")
+	     (match_operand:V_VLSF 4 "register_operand"  " vr, vr, vr, vr")] VCOPYSIGNS)
+	  (match_operand:V_VLSF 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "vfsgnj<nx>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vfsgnj")
@@ -6207,8 +6207,8 @@ (define_insn "@pred_ncopysign<mode>"
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_<copysign><mode>_scalar"
-  [(set (match_operand:VF 0 "register_operand"           "=vd, vd, vr, vr")
-	(if_then_else:VF
+  [(set (match_operand:V_VLSF 0 "register_operand"       "=vd, vd, vr, vr")
+	(if_then_else:V_VLSF
 	  (unspec:<VM>
 	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
 	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
@@ -6217,11 +6217,11 @@ (define_insn "@pred_<copysign><mode>_scalar"
 	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VF
-	    [(match_operand:VF 3 "register_operand"      " vr, vr, vr, vr")
-	     (vec_duplicate:VF
+	  (unspec:V_VLSF
+	    [(match_operand:V_VLSF 3 "register_operand"  " vr, vr, vr, vr")
+	     (vec_duplicate:V_VLSF
 	       (match_operand:<VEL> 4 "register_operand" "  f,  f,  f,  f"))] VCOPYSIGNS)
-	  (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
+	  (match_operand:V_VLSF 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "vfsgnj<nx>.vf\t%0,%3,%4%p1"
   [(set_attr "type" "vfsgnj")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 2e07e908736..c7df879dbde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -175,6 +175,14 @@ typedef double v512df __attribute__ ((vector_size (4096)));
       a[i] = CALL (b[i], c[i]);                                                \
   }
 
+#define DEF_CALL_VX(PREFIX, NUM, TYPE, CALL)                                   \
+  void __attribute__ ((noinline, noclone))                                     \
+  PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE c)            \
+  {                                                                            \
+    for (int i = 0; i < NUM; ++i)                                              \
+      a[i] = CALL (b[i], c);                                                   \
+  }
+
 #define DEF_CONST(TYPE, VAL, NUM)                                              \
   void const_##TYPE##_##NUM (TYPE *restrict a)                                 \
   {                                                                            \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
new file mode 100644
index 00000000000..0cc18d91215
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+
+DEF_CALL_VV (sgnj, 1, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 2, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 4, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 8, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 16, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 32, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 64, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 128, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 256, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 512, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 1024, _Float16, __builtin_copysignf16)
+DEF_CALL_VV (sgnj, 2048, _Float16, __builtin_copysignf16)
+
+DEF_CALL_VV (sgnj, 1, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 2, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 4, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 8, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 16, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 32, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 64, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 128, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 256, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 512, float, __builtin_copysignf)
+DEF_CALL_VV (sgnj, 1024, float, __builtin_copysignf)
+
+DEF_CALL_VV (sgnj, 1, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 2, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 4, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 8, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 16, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 32, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 64, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 128, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 256, double, __builtin_copysign)
+DEF_CALL_VV (sgnj, 512, double, __builtin_copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnj\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
new file mode 100644
index 00000000000..3a66481070a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+
+DEF_CALL_VX (sgnj, 1, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 2, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 4, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 8, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 16, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 32, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 64, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 128, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 256, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 512, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 1024, _Float16, __builtin_copysignf16)
+DEF_CALL_VX (sgnj, 2048, _Float16, __builtin_copysignf16)
+
+DEF_CALL_VX (sgnj, 1, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 2, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 4, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 8, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 16, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 32, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 64, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 128, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 256, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 512, float, __builtin_copysignf)
+DEF_CALL_VX (sgnj, 1024, float, __builtin_copysignf)
+
+DEF_CALL_VX (sgnj, 1, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 2, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 4, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 8, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 16, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 32, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 64, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 128, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 256, double, __builtin_copysign)
+DEF_CALL_VX (sgnj, 512, double, __builtin_copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnj\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
