From patchwork Fri Sep 1 05:45:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lehua Ding X-Patchwork-Id: 137371 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c792:0:b0:3f2:4152:657d with SMTP id b18csp684234vqu; Thu, 31 Aug 2023 22:49:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEBAnILDKE+jAa9H8Bkpjf5EomC8AUNwhWpywx3dnZNxIEBqWPps+8iL9eO0RM81SEDTF+b X-Received: by 2002:aa7:d316:0:b0:52c:164:efe5 with SMTP id p22-20020aa7d316000000b0052c0164efe5mr996221edq.39.1693547343135; Thu, 31 Aug 2023 22:49:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693547343; cv=none; d=google.com; s=arc-20160816; b=STxIXhhiB9g1I4uApZFkbRQtAo1TEVpt0kxJzROFcIAhPuig4IYzfZKCLxYLWeOdhl 1s2WQOE+Yo8397y46c+dFNy1xB9gxAgjEvdNacDFJeaw951WOtteSr/AOoH0e2+rp/bw IgF/zoPVPbo9f2rwNHMziNghsPVABzba3aA+iWELtS5xnS4uxgnEOLlRYR8up5Hm1ufF hmUhGfzDlg7C7iNszr6vrHhOn7fui2dKOB/lu0VUV2Zwq1+o28sGydr0WBpJsR7tfruD Emj7u6xdSLEZasa55GOI8ewKbuKP2fjb6fe74pus18wKnx5f5fER8SpkWvVfOgy/EHxY 8d3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dmarc-filter:delivered-to; bh=6tEwKNRBqWtbE4Nc56v/d0z5SReWaSENVX1v0+5gkBA=; fh=Hv/nI5qP6O0+cdTY9IQId7SAFjsbOcYYRkS818iLi4E=; b=pT0NMUQ+r9cdMGD2mUeDUvTRQ3SO/+WYN4fKCB0Zir5QRZH9GI0cQ05ddcpSPhz1kv MPPPLCHoxhPE6BkYLcMObqg7uvytpRtJIhvnm1xESoXUCYWh2A5vzYnJfDZVnlMdPVyH dfUx1YYbgcuK13+BLFolvsuWpJtIyqRhriCUov78AK+HINYsW7mU9qR9Zl00Mv4i0HlT CkokIOToXjM31o1ljzSQGY5cYXtREwgbBcF4weKoammfMT3IlGrMoFUkXolrm0DiF0dM 8TQu2iR2ef4tb/bkIXL+uGqe5VzZzYvGMmqcvhzBlv+c0NZs1Y9/2abStR4dNjPSZh71 UZvQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id cm11-20020a0564020c8b00b0052c4e3d2825si925889edb.293.2023.08.31.22.49.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 22:49:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E4F99385C6F2 for ; Fri, 1 Sep 2023 05:47:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 68EC33858438 for ; Fri, 1 Sep 2023 05:46:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68EC33858438 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1693547161t2emc6kc Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 01 Sep 2023 13:46:01 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: 3wTaVWsEHF+Iss2I8/q6BCSC36u4YriowLKAjYWbHpxuJpi5/PxSrsnIqyZ8R r+68sq14jbxxf1GQ93Cb7f/Ws+ayqvAc/zVY/lX4F5bo+AjeAdzFdUetPadA9XsDCnxqH0X Ifh5foTMJAAelMgPpMaxiS2FaNT91Qq2kSlXZzNP1ghrCUJ2ffzOmWHdTV2+ZJOWxJChi6p o+MLHCNDjIMFArXdgEdH5SMcxNqow00DTgJOjFlFdgZ8cOSqYXQSElb30dVR94+tUQxjDNN 8Kai1XR0HHmdPX0caaRn1n15euilZEM82V6C8svEs88F5ePag8kBpRFxhdQkI3AES041hYL 9mDVf55qRc0HdAoSrVwlDIC6R9giDyfYwP3VkolJK5EDtVXMVLPXo960bDvPjEMIVFB8LLT r6zfOcH71RQ= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15014173632097126983 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Subject: [PATCH 3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns Date: Fri, 1 Sep 2023 13:45:50 +0800 Message-Id: <20230901054551.1953049-4-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230901054551.1953049-1-lehua.ding@rivai.ai> References: <20230901054551.1953049-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775813098861971391 X-GMAIL-MSGID: 1775813098861971391 gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_extend): New combine pattern. (*cond_trunc): Ditto. * config/riscv/autovec.md: Adjust. * config/riscv/riscv-v.cc (needs_fp_rounding): Add FP extend. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: New test. --- gcc/config/riscv/autovec-opt.md | 39 +++++++++++++++++++ gcc/config/riscv/autovec.md | 13 ++----- gcc/config/riscv/riscv-v.cc | 4 +- .../autovec/cond/cond_convert_float2float-1.h | 29 ++++++++++++++ .../autovec/cond/cond_convert_float2float-2.h | 28 +++++++++++++ .../cond/cond_convert_float2float-rv32-1.c | 9 +++++ .../cond/cond_convert_float2float-rv32-2.c | 9 +++++ .../cond/cond_convert_float2float-rv64-1.c | 9 +++++ .../cond/cond_convert_float2float-rv64-2.c | 9 +++++ .../cond/cond_convert_float2float_run-1.c | 31 +++++++++++++++ .../cond/cond_convert_float2float_run-2.c | 30 ++++++++++++++ 11 files changed, 199 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 6796239d82d..ef468bb9df7 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -824,3 +824,42 @@ riscv_vector::expand_cond_len_unop (icode, ops); DONE; }) + +;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask +(define_insn_and_split "*cond_extend" + [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand") + (if_then_else:VWEXTF_ZVFHMIN + (match_operand: 1 "register_operand") + (float_extend:VWEXTF_ZVFHMIN (match_operand: 2 "register_operand")) + (match_operand:VWEXTF_ZVFHMIN 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_extend (mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) + +;; Combine FP trunc(vf2) + vcond_mask +(define_insn_and_split "*cond_trunc" + [(set (match_operand: 0 "register_operand") + (if_then_else: + (match_operand: 1 "register_operand") + (float_truncate: + (match_operand:VWEXTF_ZVFHMIN 2 "register_operand")) + (match_operand: 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_trunc (mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_unop (icode, ops); + DONE; +}) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 4859805b8f7..a4ac688e373 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -742,13 +742,8 @@ "TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)" { rtx dblw = gen_reg_rtx (mode); - insn_code icode = code_for_pred_extend (mode); - rtx ops1[] = {dblw, operands[1]}; - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops1); - - icode = code_for_pred_extend (mode); - rtx ops2[] = {operands[0], dblw}; - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops2); + emit_insn (gen_extend2 (dblw, operands[1])); + emit_insn (gen_extend2 (operands[0], dblw)); DONE; }) @@ -791,9 +786,7 @@ insn_code icode = code_for_pred_rod_trunc (mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opshalf); - rtx ops[] = {operands[0], half}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, ops); + emit_insn (gen_trunc2 (operands[0], half)); DONE; }) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 89ac4743f40..0f414663620 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2966,7 +2966,9 @@ needs_fp_rounding (unsigned icode, machine_mode mode) return icode != maybe_code_for_pred (SMIN, mode) && icode != maybe_code_for_pred (SMAX, mode) && icode != maybe_code_for_pred (NEG, mode) - && icode != maybe_code_for_pred (ABS, mode); + && icode != maybe_code_for_pred (ABS, mode) + /* narrower-FP -> FP */ + && icode != maybe_code_for_pred_extend (mode); } /* Subroutine to expand COND_LEN_* patterns. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h new file mode 100644 index 00000000000..4742d926af6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h @@ -0,0 +1,29 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, \ + NEW_TYPE *__restrict b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \ + } \ + } + +/* FP -> wider-FP */ +#define TEST_ALL_F2F_WIDER(T) \ + T (_Float16, float) \ + T (_Float16, double) \ + T (float, double) + +/* FP -> narrower-FP */ +#define TEST_ALL_F2F_NARROWER(T) \ + T (float, _Float16) \ + T (double, _Float16) \ + T (double, float) + +TEST_ALL_F2F_WIDER (DEF_LOOP) +TEST_ALL_F2F_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h new file mode 100644 index 00000000000..b084eaae19d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h @@ -0,0 +1,28 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, NEW_TYPE b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \ + } \ + } + +/* FP -> wider-FP */ +#define TEST_ALL_F2F_WIDER(T) \ + T (_Float16, float) \ + T (_Float16, double) \ + T (float, double) + +/* FP -> narrower-FP */ +#define TEST_ALL_F2F_NARROWER(T) \ + T (float, _Float16) \ + T (double, _Float16) \ + T (double, float) + +TEST_ALL_F2F_WIDER (DEF_LOOP) +TEST_ALL_F2F_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c new file mode 100644 index 00000000000..e0d9eaa4173 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-1.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c new file mode 100644 index 00000000000..8d963b0397b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-2.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c new file mode 100644 index 00000000000..9841fdd7f79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-1.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c new file mode 100644 index 00000000000..03ee19fa9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-2.h" + +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c new file mode 100644 index 00000000000..407bbc27c2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-1.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b[N]; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_F2F_WIDER (TEST_LOOP) + TEST_ALL_F2F_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c new file mode 100644 index 00000000000..05d217da625 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2float-2.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b = 18.02; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_F2F_WIDER (TEST_LOOP) + TEST_ALL_F2F_NARROWER (TEST_LOOP) + return 0; +}