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[8.43.85.97]) by mx.google.com with ESMTPS id t20-20020a1709063e5400b00992fef5cffasi2048762eji.641.2023.08.31.22.47.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 22:47:36 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D9EEF3851C04 for ; Fri, 1 Sep 2023 05:46:35 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 0DEA0385842E for ; Fri, 1 Sep 2023 05:46:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0DEA0385842E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1693547155t5hd4yu6 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 01 Sep 2023 13:45:54 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: KzokuMsy9J0r+qmuyuB1uEbwwMpie+L0PJ0gxPcgjE22R2bJQXVzaPq/xAPCy 3xQD2p+zKChj9Abh9pOaxLLB4HrEjk6ewmgUYws3x24aiRaXFCpmlxpPBGJiW/N0B4U1UyZ 6cYmPEyzrkwGl1wdsDb5gSYDiJv6MvJQsuV5X3cUKOWllz1Hq5cZIqoJ++khsycZrurq1Sg Z5kWgmtoyFnSarBON8GGlCTq96FJ+6WCBOFK68vEKTRWzaEdaWB8oL/tPCmvD8RgPZ/HkMz 3QsgvXLuYgOGFwOckPTta3jbtJh+qSW3qNAZ3Zdmymrew77P4aHgjEQPXcHff/7ZJrH5hlx iiYjvjoTWDoZboRup+ZpO61ilZICSOqK6aRvXqS3/VakxougU4hfmNo+Z/gUDvM6Lq7nyBp 4WO6KXiZX8o= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 8267531306622387483 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Subject: [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Date: Fri, 1 Sep 2023 13:45:48 +0800 Message-Id: <20230901054551.1953049-2-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230901054551.1953049-1-lehua.ding@rivai.ai> References: <20230901054551.1953049-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775813008434546144 X-GMAIL-MSGID: 1775813008434546144 This patch change expand_cond_len_{unary,binop}'s argument `rtx_code code` to `unsigned icode` and use the icode directly to determine whether the rounding_mode operand is required. gcc/ChangeLog: * config/riscv/autovec.md: Adjust. * config/riscv/riscv-protos.h (expand_cond_len_unop): Ditto. (expand_cond_len_binop): Ditto. * config/riscv/riscv-v.cc (needs_fp_rounding): Ditto. (expand_cond_len_op): Ditto. (expand_cond_len_unop): Ditto. (expand_cond_len_binop): Ditto. (expand_cond_len_ternop): Ditto. --- gcc/config/riscv/autovec.md | 18 +++++++++++------ gcc/config/riscv/riscv-protos.h | 4 ++-- gcc/config/riscv/riscv-v.cc | 34 +++++++++++++++++++-------------- 3 files changed, 34 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index ebe1b10aa12..006e174ebd5 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1551,7 +1551,8 @@ (match_operand 5 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_unop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_unop (icode, operands); DONE; }) @@ -1588,7 +1589,8 @@ (match_operand 5 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_unop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_unop (icode, operands); DONE; }) @@ -1627,7 +1629,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1667,7 +1670,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1707,7 +1711,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) @@ -1745,7 +1750,8 @@ (match_operand 6 "const_0_operand")] "TARGET_VECTOR" { - riscv_vector::expand_cond_len_binop (, operands); + insn_code icode = code_for_pred (, mode); + riscv_vector::expand_cond_len_binop (icode, operands); DONE; }) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index e145ee6c69b..dd7aa360ec5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -426,8 +426,8 @@ bool neg_simm5_p (rtx); bool has_vi_variant_p (rtx_code, rtx); void expand_vec_cmp (rtx, rtx_code, rtx, rtx); bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); -void expand_cond_len_unop (rtx_code, rtx *); -void expand_cond_len_binop (rtx_code, rtx *); +void expand_cond_len_unop (unsigned, rtx *); +void expand_cond_len_binop (unsigned, rtx *); void expand_reduction (rtx_code, rtx *, rtx, reduction_type = reduction_type::UNORDERED); #endif diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 6228ff3d92e..89ac4743f40 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -245,6 +245,12 @@ public: always Pmode. */ if (mode == VOIDmode) mode = Pmode; + else + /* Early assertion ensures same mode since maybe_legitimize_operand + will check this. */ + gcc_assert (GET_MODE (ops[opno]) == VOIDmode + || GET_MODE (ops[opno]) == mode); + add_input_operand (ops[opno], mode); } @@ -291,6 +297,7 @@ public: if (m_insn_flags & FRM_DYN_P) add_rounding_mode_operand (FRM_DYN); + gcc_assert (insn_data[(int) icode].n_operands == m_opno); expand (icode, any_mem_p); } @@ -2951,17 +2958,20 @@ expand_load_store (rtx *ops, bool is_load) /* Return true if the operation is the floating-point operation need FRM. */ static bool -needs_fp_rounding (rtx_code code, machine_mode mode) +needs_fp_rounding (unsigned icode, machine_mode mode) { if (!FLOAT_MODE_P (mode)) return false; - return code != SMIN && code != SMAX && code != NEG && code != ABS; + + return icode != maybe_code_for_pred (SMIN, mode) + && icode != maybe_code_for_pred (SMAX, mode) + && icode != maybe_code_for_pred (NEG, mode) + && icode != maybe_code_for_pred (ABS, mode); } /* Subroutine to expand COND_LEN_* patterns. */ static void -expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, - rtx len) +expand_cond_len_op (unsigned icode, insn_flags op_type, rtx *ops, rtx len) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -2980,7 +2990,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, else insn_flags |= TU_POLICY_P | MU_POLICY_P; - if (needs_fp_rounding (code, mode)) + if (needs_fp_rounding (icode, mode)) insn_flags |= FRM_DYN_P; if (is_vlmax_len) @@ -2991,7 +3001,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops, /* Expand unary ops COND_LEN_*. */ void -expand_cond_len_unop (rtx_code code, rtx *ops) +expand_cond_len_unop (unsigned icode, rtx *ops) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -2999,15 +3009,13 @@ expand_cond_len_unop (rtx_code code, rtx *ops) rtx merge = ops[3]; rtx len = ops[4]; - machine_mode mode = GET_MODE (dest); - insn_code icode = code_for_pred (code, mode); rtx cond_ops[] = {dest, mask, merge, src}; - expand_cond_len_op (code, icode, UNARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len); } /* Expand binary ops COND_LEN_*. */ void -expand_cond_len_binop (rtx_code code, rtx *ops) +expand_cond_len_binop (unsigned icode, rtx *ops) { rtx dest = ops[0]; rtx mask = ops[1]; @@ -3016,10 +3024,8 @@ expand_cond_len_binop (rtx_code code, rtx *ops) rtx merge = ops[4]; rtx len = ops[5]; - machine_mode mode = GET_MODE (dest); - insn_code icode = code_for_pred (code, mode); rtx cond_ops[] = {dest, mask, merge, src1, src2}; - expand_cond_len_op (code, icode, BINARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len); } /* Prepare insn_code for gather_load/scatter_store according to @@ -3191,7 +3197,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) rtx len = ops[6]; rtx cond_ops[] = {dest, mask, src1, src2, src3, merge}; - expand_cond_len_op (UNSPEC, icode, TERNARY_OP_P, cond_ops, len); + expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len); } /* Expand reduction operations. */