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[8.43.85.97]) by mx.google.com with ESMTPS id w4-20020a056402128400b0052a10293879si653486edv.446.2023.08.31.01.22.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 01:22:43 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=F6I5F5yf; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 755FC3856944 for ; Thu, 31 Aug 2023 08:21:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 755FC3856944 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693470093; bh=VIf0mism40fFWcCGrnTAwdsJzGYGWOs+ybqn4iae3E4=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=F6I5F5yfHjB9cLWaQxUKWD/Swl26Fb2x6d6QVwYe+0eKhkHkSr6AcGXIfC+BHTF8t 6s7UHjBxcqAOw2VPcIQkku5O0xg7bJooyiDvOFRfZND6cIfFBC6Qq/pRfGpQtfPDv5 ZtAFnnwa+6Mf19+XIArab54WqPeIMPNZXBI6XP0c= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 21CD13858C2B for ; Thu, 31 Aug 2023 08:20:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 21CD13858C2B X-IronPort-AV: E=McAfee;i="6600,9927,10818"; a="462235572" X-IronPort-AV: E=Sophos;i="6.02,216,1688454000"; d="scan'208";a="462235572" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 01:20:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10818"; a="862938619" X-IronPort-AV: E=Sophos;i="6.02,216,1688454000"; d="scan'208";a="862938619" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 31 Aug 2023 01:20:25 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7C119100519E; Thu, 31 Aug 2023 16:20:24 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH 02/13] [APX EGPR] middle-end: Add index_reg_class with insn argument. Date: Thu, 31 Aug 2023 16:20:13 +0800 Message-Id: <20230831082024.314097-3-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230831082024.314097-1-hongyu.wang@intel.com> References: <20230831082024.314097-1-hongyu.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hongyu Wang via Gcc-patches From: Hongyu Wang Reply-To: Hongyu Wang Cc: jakub@redhat.com, hongtao.liu@intel.com, hubicka@ucw.cz Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775732169929671993 X-GMAIL-MSGID: 1775732169929671993 Like base_reg_class, INDEX_REG_CLASS also does not support backend insn. Add index_reg_class with insn argument for lra/reload usage. gcc/ChangeLog: * addresses.h (index_reg_class): New wrapper function like base_reg_class. * doc/tm.texi: Document INSN_INDEX_REG_CLASS. * doc/tm.texi.in: Ditto. * lra-constraints.cc (index_part_to_reg): Pass index_class. (process_address_1): Calls index_reg_class with curr_insn and replace INDEX_REG_CLASS with its return value index_cl. * reload.cc (find_reloads_address): Likewise. (find_reloads_address_1): Likewise. --- gcc/addresses.h | 10 ++++++++++ gcc/doc/tm.texi | 9 +++++++++ gcc/doc/tm.texi.in | 9 +++++++++ gcc/lra-constraints.cc | 17 +++++++++-------- gcc/reload.cc | 4 ++-- 5 files changed, 39 insertions(+), 10 deletions(-) diff --git a/gcc/addresses.h b/gcc/addresses.h index 08b100cfe6d..4bd96a3fc83 100644 --- a/gcc/addresses.h +++ b/gcc/addresses.h @@ -47,6 +47,16 @@ base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, #endif } +inline enum reg_class +index_reg_class (rtx_insn *insn ATTRIBUTE_UNUSED = NULL) +{ +#ifdef INSN_INDEX_REG_CLASS + return INSN_INDEX_REG_CLASS (insn); +#else + return INDEX_REG_CLASS; +#endif +} + /* Wrapper function to unify target macros REGNO_MODE_CODE_OK_FOR_BASE_P, REGNO_MODE_OK_FOR_REG_BASE_P, REGNO_MODE_OK_FOR_BASE_P and REGNO_OK_FOR_BASE_P. diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index a4239e3de10..5a50f5cf7f3 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -2553,6 +2553,15 @@ address where its value is either multiplied by a scale factor or added to another register (as well as added to a displacement). @end defmac +@defmac INSN_INDEX_REG_CLASS (@var{insn}) +A C expression whose value is the register class to which a valid +index register must belong. An index register is one used in an +address where its value is either multiplied by a scale factor or +added to another register (as well as added to a displacement). +@code{insn} indicates insn specific index register class should be +subset of the original index register class. +@end defmac + @defmac REGNO_OK_FOR_BASE_P (@var{num}) A C expression which is nonzero if register number @var{num} is suitable for use as a base register in operand addresses. diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 72898f3adba..65748e19ccd 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -2148,6 +2148,15 @@ address where its value is either multiplied by a scale factor or added to another register (as well as added to a displacement). @end defmac +@defmac INSN_INDEX_REG_CLASS (@var{insn}) +A C expression whose value is the register class to which a valid +index register must belong. An index register is one used in an +address where its value is either multiplied by a scale factor or +added to another register (as well as added to a displacement). +@code{insn} indicates insn specific index register class should be +subset of the original index register class. +@end defmac + @defmac REGNO_OK_FOR_BASE_P (@var{num}) A C expression which is nonzero if register number @var{num} is suitable for use as a base register in operand addresses. diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 9e7915ce934..161b67d8b73 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -3390,12 +3390,12 @@ base_plus_disp_to_reg (struct address_info *ad, rtx disp) /* Make reload of index part of address AD. Return the new pseudo. */ static rtx -index_part_to_reg (struct address_info *ad) +index_part_to_reg (struct address_info *ad, enum reg_class index_class) { rtx new_reg; new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, - INDEX_REG_CLASS, NULL, "index term"); + index_class, NULL, "index term"); expand_mult (GET_MODE (*ad->index), *ad->index_term, GEN_INT (get_index_scale (ad)), new_reg, 1); return new_reg; @@ -3650,13 +3650,14 @@ process_address_1 (int nop, bool check_only_p, /* If INDEX_REG_CLASS is assigned to base_term already and isn't to index_term, swap them so to avoid assigning INDEX_REG_CLASS to both when INDEX_REG_CLASS is a single register class. */ + enum reg_class index_cl = index_reg_class (curr_insn); if (ad.base_term != NULL && ad.index_term != NULL - && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 + && ira_class_hard_regs_num[index_cl] == 1 && REG_P (*ad.base_term) && REG_P (*ad.index_term) - && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) - && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) + && in_class_p (*ad.base_term, index_cl, NULL) + && ! in_class_p (*ad.index_term, index_cl, NULL)) { std::swap (ad.base, ad.index); std::swap (ad.base_term, ad.index_term); @@ -3680,7 +3681,7 @@ process_address_1 (int nop, bool check_only_p, } if (ad.index_term != NULL && process_addr_reg (ad.index_term, check_only_p, - before, NULL, INDEX_REG_CLASS)) + before, NULL, index_cl)) change_p = true; /* Target hooks sometimes don't treat extra-constraint addresses as @@ -3789,7 +3790,7 @@ process_address_1 (int nop, bool check_only_p, GET_CODE (*ad.index), curr_insn); - lra_assert (INDEX_REG_CLASS != NO_REGS); + lra_assert (index_cl != NO_REGS); new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "disp"); lra_emit_move (new_reg, *ad.disp); *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), @@ -3885,7 +3886,7 @@ process_address_1 (int nop, bool check_only_p, changed pseudo on the equivalent memory and a subreg of the pseudo onto the memory of different mode for which the scale is prohibitted. */ - new_reg = index_part_to_reg (&ad); + new_reg = index_part_to_reg (&ad, index_cl); *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), *ad.base_term, new_reg); } diff --git a/gcc/reload.cc b/gcc/reload.cc index 72f7e27af15..66b484b12fa 100644 --- a/gcc/reload.cc +++ b/gcc/reload.cc @@ -5114,7 +5114,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad, /* Reload the displacement into an index reg. We assume the frame pointer or arg pointer is a base reg. */ find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), - INDEX_REG_CLASS, GET_MODE (ad), opnum, + index_reg_class (insn), GET_MODE (ad), opnum, type, ind_levels); return 0; } @@ -5514,7 +5514,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as, bool reloaded_inner_of_autoinc = false; if (context == 1) - context_reg_class = INDEX_REG_CLASS; + context_reg_class = index_reg_class (insn); else context_reg_class = base_reg_class (mode, as, outer_code, index_code, insn);