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[8.43.85.97]) by mx.google.com with ESMTPS id e18-20020a170906249200b00992bf8cc68csi5284837ejb.973.2023.08.29.18.58.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 18:58:26 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3A2283853D16 for ; Wed, 30 Aug 2023 01:56:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id AC8783858C30 for ; Wed, 30 Aug 2023 01:55:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AC8783858C30 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1693360497td1k6kek Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 30 Aug 2023 09:54:57 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: BfD0FmxEGeCBgkqt4jZK5LENiehDmeOeH8KyKJh7cvj4lO0t9SVTTH/8Q0OUj 0OihGrKnsz2rfGpT7LFfQyw3Uwn45FUExlGC60+L001iyHDL7KNeah3QIYOWvRFTKiHCi9+ aF/ilT590dfo+IytbYk5mSc22vo02BBK355iZBF5sQo5837seK4iFdv36egQbZS5LVebbbZ J/GYe1xYquk8HW3qZ1IMmGASlHF095zfxHdOw0FxkePGbVnr9hJRivTDYmHZnBZ7uLKfODX iNZgsyj8m5QI7RLDNRG+laBx3Q1h0wj2JXFpz0u9+agmftYf0ty7wZt6QAnS/Rsl2OVr7at MpMEpKPatR08ucQG60gVnE1VMY/y+/wEKAKGv0i3jt5jgoDuicQY5ysg3nlRA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6931338135723656172 From: Lehua Ding To: gcc-patches@gcc.gnu.org Subject: [PATCH V3 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function Date: Wed, 30 Aug 2023 09:54:45 +0800 Message-Id: <20230830015445.597055-4-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230830015445.597055-1-lehua.ding@rivai.ai> References: <20230830015445.597055-1-lehua.ding@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775617396092580283 X-GMAIL-MSGID: 1775617396092580283 Functions which follow vector calling convention variant need be annotated by .variant_cc directive according the RISC-V Assembly Programmer's Manual[1] and RISC-V ELF Specification[2]. [1] https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops [2] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#dynamic-linking gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_declare_function_name): Add protos. (riscv_asm_output_alias): Ditto. (riscv_asm_output_external): Ditto. * config/riscv/riscv.cc (riscv_asm_output_variant_cc): Output .variant_cc directive for vector function. (riscv_declare_function_name): Ditto. (riscv_asm_output_alias): Ditto. (riscv_asm_output_external): Ditto. * config/riscv/riscv.h (ASM_DECLARE_FUNCTION_NAME): Implement ASM_DECLARE_FUNCTION_NAME. (ASM_OUTPUT_DEF_FROM_DECLS): Implement ASM_OUTPUT_DEF_FROM_DECLS. (ASM_OUTPUT_EXTERNAL): Implement ASM_OUTPUT_EXTERNAL. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-call-variant_cc.c: New test. --- gcc/config/riscv/riscv-protos.h | 3 ++ gcc/config/riscv/riscv.cc | 48 +++++++++++++++++++ gcc/config/riscv/riscv.h | 15 ++++++ .../riscv/rvv/base/abi-call-variant_cc.c | 39 +++++++++++++++ 4 files changed, 105 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 4ac4de18cbe..16139b4d0de 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -102,6 +102,9 @@ extern bool riscv_split_64bit_move_p (rtx, rtx); extern void riscv_split_doubleword_move (rtx, rtx); extern const char *riscv_output_move (rtx, rtx); extern const char *riscv_output_return (); +extern void riscv_declare_function_name (FILE *, const char *, tree); +extern void riscv_asm_output_alias (FILE *, const tree, const tree); +extern void riscv_asm_output_external (FILE *, const tree, const char *); #ifdef RTX_CODE extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 382b1d096b5..bf6f54e71fd 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7335,6 +7335,54 @@ riscv_emit_attribute () riscv_stack_boundary / 8); } +/* Output .variant_cc for function symbol which follows vector calling + convention. */ + +static void +riscv_asm_output_variant_cc (FILE *stream, const tree decl, const char *name) +{ + if (TREE_CODE (decl) == FUNCTION_DECL) + { + riscv_cc cc = (riscv_cc) fndecl_abi (decl).id (); + if (cc == RISCV_CC_V) + { + fprintf (stream, "\t.variant_cc\t"); + assemble_name (stream, name); + fprintf (stream, "\n"); + } + } +} + +/* Implement ASM_DECLARE_FUNCTION_NAME. */ + +void +riscv_declare_function_name (FILE *stream, const char *name, tree fndecl) +{ + riscv_asm_output_variant_cc (stream, fndecl, name); + ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function"); + ASM_OUTPUT_LABEL (stream, name); +} + +/* Implement ASM_OUTPUT_DEF_FROM_DECLS. */ + +void +riscv_asm_output_alias (FILE *stream, const tree decl, const tree target) +{ + const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0); + const char *value = IDENTIFIER_POINTER (target); + riscv_asm_output_variant_cc (stream, decl, name); + ASM_OUTPUT_DEF (stream, name, value); +} + +/* Implement ASM_OUTPUT_EXTERNAL. */ + +void +riscv_asm_output_external (FILE *stream, tree decl, const char *name) +{ + default_elf_asm_output_external (stream, decl, name); + riscv_asm_output_variant_cc (stream, decl, name); +} + /* Implement TARGET_ASM_FILE_START. */ static void diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 926465e70a0..30961c7a8ac 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1021,6 +1021,21 @@ while (0) #define ASM_COMMENT_START "#" +/* Add output .variant_cc directive for specific function definition. */ +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ + riscv_declare_function_name (STR, NAME, DECL) + +/* Add output .variant_cc directive for specific alias definition. */ +#undef ASM_OUTPUT_DEF_FROM_DECLS +#define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ + riscv_asm_output_alias (STR, DECL, TARGET) + +/* Add output .variant_cc directive for specific extern function. */ +#undef ASM_OUTPUT_EXTERNAL +#define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ + riscv_asm_output_external (STR, DECL, NAME) + #undef SIZE_TYPE #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c new file mode 100644 index 00000000000..4e45203f5b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +f_undef1 (vint8m1_t a); +void +f_undef2 (vint8m1x8_t a); +void +f_undef3 (vbool1_t a); +vint8m1_t +f_undef4 (); + +void +bar_real (vint8m1_t a, vint8m1x8_t b, vbool1_t c) +{ + f_undef1 (a); + f_undef2 (b); + f_undef3 (c); +} + +__attribute__ ((alias ("bar_real"))) void +bar_alias (vint8m1_t a, vint8m1x8_t b, vbool1_t c); + +void +f_1 (vint8m1_t *a, vint8m1x8_t *b, vbool1_t *c) +{ + bar_alias (*a, *b, *c); + *a = f_undef4 (); +} + +/* { dg-final { scan-assembler-times {\.variant_cc\tbar_real} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tbar_alias} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_1} 0 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef1} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef2} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef3} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tf_undef4} 1 } } */