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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d17-20020a170906371100b0099bbf89772bsi3974577ejc.757.2023.08.29.03.50.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 03:50:48 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ZFHhuf0h; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ADC223858C30 for ; Tue, 29 Aug 2023 10:50:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ADC223858C30 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693306246; bh=jQGJKp6vGiKPEE1p3n8ISeHW4tK7BlX/nUmEBJSNO0k=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=ZFHhuf0hmflA6PD1ICiN2PpCZNbgbnN0m/ZxMk5mEP1p5N8KZUP/+X94jw9MZab57 urk0CKUtyDv6Z2lDfjXs+9FDr0RdYrS6ucKZDp4EYBW2J45wqTR6RrnJAh5yR1dHDr tKLP/jaWJiXsc7vUtd+X1jQ2AL155InEYnO2IYM4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id B8FC23858D33 for ; Tue, 29 Aug 2023 10:49:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B8FC23858D33 X-IronPort-AV: E=McAfee;i="6600,9927,10816"; a="441689338" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441689338" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 03:49:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10816"; a="688457381" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688457381" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 03:49:23 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 895D01005613; Tue, 29 Aug 2023 18:49:22 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH v1] RISC-V: Fix one ICE for vect test vect-multitypes-5 Date: Tue, 29 Aug 2023 18:49:21 +0800 Message-Id: <20230829104921.4117031-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Cc: yanzhang.wang@intel.com, kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775560292246370488 X-GMAIL-MSGID: 1775560292246370488 From: Pan Li There will be one ICE when build vect-multitypes-5.c similar as below: riscv64-unknown-elf-gcc -O3 \ -march=rv64imafdcv -mabi=lp64d -mcmodel=medlow \ -fdiagnostics-plain-output -flto -ffat-lto-objects \ --param riscv-autovec-preference=scalable -Wno-psabi \ -ftree-vectorize -fno-tree-loop-distribute-patterns \ -fno-vect-cost-model -fno-common -O2 -fdump-tree-vect-details \ gcc/testsuite/gcc.dg/vect/vect-multitypes-5.c -o test.elf -lm The below RTL is not well handled in riscv_legitimize_const_move, and then fall through to the default pass. Then the default force_const_mem will NULL_RTX, and will have ICE when operating one the NULL_RTX. (const:DI (plus:DI (symbol_ref:DI ("ic") [flags 0x2] ) (const_poly_int:DI [16, 16]))) This patch would like to take care of this rtl in riscv_legitimize_const_move. Signed-off-by: Pan Li Co-Authored-By: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_poly_move): New declaration. (riscv_legitimize_const_move): Handle ref plus const poly. --- gcc/config/riscv/riscv.cc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1d6e278ea90..bab6ed70b2d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -366,6 +366,7 @@ static const struct riscv_tune_param optimize_size_tune_info = { static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); +static void riscv_legitimize_poly_move (machine_mode, rtx, rtx, rtx); /* Defining target-specific uses of __attribute__. */ static const struct attribute_spec riscv_attribute_table[] = @@ -2118,6 +2119,28 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) return; } + /* Handle below format. + (const:DI + (plus:DI + (symbol_ref:DI ("ic") [flags 0x2] ) <- op_0 + (const_poly_int:DI [16, 16]) // <- op_1 + )) + */ + rtx src_op_0 = XEXP (src, 0); + + if (GET_CODE (src) == CONST && GET_CODE (src_op_0) == PLUS + && CONST_POLY_INT_P (XEXP (src_op_0, 1))) + { + rtx dest_tmp = gen_reg_rtx (mode); + rtx tmp = gen_reg_rtx (mode); + + riscv_emit_move (dest, XEXP (src_op_0, 0)); + riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (src_op_0, 1)); + + emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, dest, dest_tmp))); + return; + } + src = force_const_mem (mode, src); /* When using explicit relocs, constant pool references are sometimes