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[8.43.85.97]) by mx.google.com with ESMTPS id x12-20020a1709065acc00b0098734429161si5510456ejs.181.2023.08.21.00.27.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Aug 2023 00:27:25 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=v2IneVfS; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AB9033857357 for ; Mon, 21 Aug 2023 07:27:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AB9033857357 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692602844; bh=xSnrFVxyaItvygPD/x/oIzxe7xh3xsnL0wRD+/ts+kQ=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=v2IneVfSFo27OUeRGo5hsyC8ixpN3yx3W+pZ0ajnLN6l2+k9W3GpTQcQhsHulz0at ox47Q1VfBipupZWcc+4uw8Avn4LwNYcFvv6hivr3GeVYwIHaUDheVkgKHsyRVlbNP0 6lmubqLHm3zRVVEswYYAkaElRGF04vPLgxeINf3I= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 7E4933858291 for ; Mon, 21 Aug 2023 07:26:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7E4933858291 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="370953363" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="370953363" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 00:26:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="735766732" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="735766732" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 21 Aug 2023 00:26:30 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id BD056100560B; Mon, 21 Aug 2023 15:26:29 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook Date: Mon, 21 Aug 2023 15:26:27 +0800 Message-Id: <20230821072627.3984748-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774822721866923210 X-GMAIL-MSGID: 1774822721866923210 From: Pan Li We have EMIT hook in mode switching already, which will insert the insn before in most cases. However, in some arch like RISC-V, it requires the additional insn to be inserted after when meet a call. | | <- EMIT HOOK, insert the insn before. +-----------+ | ptr->insn | +-----------+ | <- EMIT_AFTER HOOK, insert the insn after. | Thus, this patch would like to add one optional EMIT_AFTER hook, which will try to insert the emitted insn after. The end-user can either implement this HOOK or leave it NULL as is. If the backend ignore this optinal hook, there is no impact to the original mode switching stuff. If the backend implement this optional hook, the mode switching will try to insert the insn after. Please note the EMIT_AFTER doen't have any impact to EMIT hook. Passed both the regression and bootstrap test in x86. Signed-off-by: Pan Li gcc/ChangeLog: * doc/tm.texi: Add hook def and update the description. * doc/tm.texi.in: Ditto. * mode-switching.cc (optimize_mode_switching): Insert the emitted insn after ptr->insn. * target.def (insn): Define emit_after hook. --- gcc/doc/tm.texi | 12 ++++++++++-- gcc/doc/tm.texi.in | 6 ++++-- gcc/mode-switching.cc | 45 +++++++++++++++++++++++++++++++++++++++++++ gcc/target.def | 9 +++++++++ 4 files changed, 68 insertions(+), 4 deletions(-) diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index e4d0cc43f41..a0798d4468b 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -10334,8 +10334,8 @@ return nonzero for any @var{entity} that needs mode-switching. If you define this macro, you also have to define @code{NUM_MODES_FOR_MODE_SWITCHING}, @code{TARGET_MODE_NEEDED}, @code{TARGET_MODE_PRIORITY} and @code{TARGET_MODE_EMIT}. -@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, and @code{TARGET_MODE_EXIT} -are optional. +@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, @code{TARGET_MODE_EMIT_AFTER}, +and @code{TARGET_MODE_EXIT} are optional. @end defmac @defmac NUM_MODES_FOR_MODE_SWITCHING @@ -10359,6 +10359,14 @@ to switch from. Sets of a lower numbered entity will be emitted before sets of a higher numbered entity to a mode of the same or lower priority. @end deftypefn +@deftypefn {Target Hook} void TARGET_MODE_EMIT_AFTER (int @var{entity}, int @var{mode}, int @var{prev_mode}, HARD_REG_SET @var{regs_live}) +Generate one or more insns to set @var{entity} to @var{mode}. +@var{hard_reg_live} is the set of hard registers live at the point where +the insn(s) are to be inserted after. @var{prev_moxde} indicates the mode +to switch from. Sets of a lower numbered entity will be emitted before +sets of a higher numbered entity to a mode of the same or lower priority. +@end deftypefn + @deftypefn {Target Hook} int TARGET_MODE_NEEDED (int @var{entity}, rtx_insn *@var{insn}) @var{entity} is an integer specifying a mode-switched entity. If @code{OPTIMIZE_MODE_SWITCHING} is defined, you must define this macro diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 4ac96dc357d..2942ce0be3b 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -6911,8 +6911,8 @@ return nonzero for any @var{entity} that needs mode-switching. If you define this macro, you also have to define @code{NUM_MODES_FOR_MODE_SWITCHING}, @code{TARGET_MODE_NEEDED}, @code{TARGET_MODE_PRIORITY} and @code{TARGET_MODE_EMIT}. -@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, and @code{TARGET_MODE_EXIT} -are optional. +@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, @code{TARGET_MODE_EMIT_AFTER}, +and @code{TARGET_MODE_EXIT} are optional. @end defmac @defmac NUM_MODES_FOR_MODE_SWITCHING @@ -6930,6 +6930,8 @@ switch is needed / supplied. @hook TARGET_MODE_EMIT +@hook TARGET_MODE_EMIT_AFTER + @hook TARGET_MODE_NEEDED @hook TARGET_MODE_AFTER diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc index f483c831c35..98051dff487 100644 --- a/gcc/mode-switching.cc +++ b/gcc/mode-switching.cc @@ -34,6 +34,8 @@ along with GCC; see the file COPYING3. If not see #include "lcm.h" #include "cfgcleanup.h" #include "tree-pass.h" +#include "cfgbuild.h" +#include "gcse.h" /* We want target macros for the mode switching code to be able to refer to instruction attribute values. */ @@ -831,6 +833,49 @@ optimize_mode_switching (void) emit_insn_before (mode_set, ptr->insn_ptr); } + if (targetm.mode_switching.emit_after) + { + if (control_flow_insn_p (ptr->insn_ptr) + && ptr->insn_ptr == BB_END (bb)) + { + edge eg; + edge_iterator eg_iterator; + + FOR_EACH_EDGE (eg, eg_iterator, bb->succs) + { + start_sequence (); + targetm.mode_switching.emit_after (entity_map[j], + ptr->mode, cur_mode, ptr->regs_live); + mode_set = get_insns (); + end_sequence (); + + if (mode_set != NULL_RTX) + { + if (eg->flags & EDGE_ABNORMAL) + insert_insn_end_basic_block (mode_set, bb); + else + insert_insn_on_edge (mode_set, eg); + + emitted = true; + need_commit = true; + } + } + } + else + { + start_sequence (); + targetm.mode_switching.emit_after (entity_map[j], + ptr->mode, cur_mode, ptr->regs_live); + mode_set = get_insns (); + end_sequence (); + + if (mode_set != NULL_RTX) + { + emit_insn_after (mode_set, ptr->insn_ptr); + emitted = true; + } + } + } default_rtl_profile (); } diff --git a/gcc/target.def b/gcc/target.def index a500aeb6714..abcf9dc5c0e 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -7005,6 +7005,15 @@ to switch from. Sets of a lower numbered entity will be emitted before\n\ sets of a higher numbered entity to a mode of the same or lower priority.", void, (int entity, int mode, int prev_mode, HARD_REG_SET regs_live), NULL) +DEFHOOK +(emit_after, + "Generate one or more insns to set @var{entity} to @var{mode}.\n\ +@var{hard_reg_live} is the set of hard registers live at the point where\n\ +the insn(s) are to be inserted after. @var{prev_moxde} indicates the mode\n\ +to switch from. Sets of a lower numbered entity will be emitted before\n\ +sets of a higher numbered entity to a mode of the same or lower priority.", + void, (int entity, int mode, int prev_mode, HARD_REG_SET regs_live), NULL) + DEFHOOK (needed, "@var{entity} is an integer specifying a mode-switched entity.\n\