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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id gx21-20020a170906f1d500b009a179f2902fsi2615327ejb.721.2023.08.20.18.04.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Aug 2023 18:04:43 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 71F2C3836E93 for ; Mon, 21 Aug 2023 01:04:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 63E903858C78 for ; Mon, 21 Aug 2023 01:03:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 63E903858C78 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp74t1692579811thybwqpb Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.7]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 21 Aug 2023 09:03:30 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: C46Rb8GPIEfh6lEtJnQpMz97tCMvJqvdevl1I2rh3LDz48YI9ZC9BUkOYg0LS 01Z8ORGgOi6ja+VSBpoA/HP30CpPyhkCfTXbrLzScUOCVSO+k31XZ7XPRTXzwN5t9o+pt4U XgqQKuCcBYCr/LKb1eYAUZygKSZi6OgP0v7gbd3bM9r+Rr3gcU05toO6qQf++zfRPbR/REe 7xoJMtXHfaMJvmOYhRmcq22iJybXGegVdt7EKNnejDaHkkdLJMojIMq6WN7N4rtmG40V/X7 qmgjYlvOuDFjbSELsklRAcy8bPtAkNTd1kg1Buq+Myl8ySLr6hu6ZORadJ1Ac1sMENFV0fi BuAiMsASNXRDbDvmMRmYihdR2u6fSpGyqR5h4jW X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17301368461519756404 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: rguenther@suse.de, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037] Date: Mon, 21 Aug 2023 09:03:26 +0800 Message-Id: <20230821010326.395043-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774798643804452961 X-GMAIL-MSGID: 1774798643804452961 void foo(_Float16 y, int64_t *i64p) { vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1); vx = __riscv_vadd_vv_i64m1 (vx, vx, 1); vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1); asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy)); } zve64f: foo: vsetivli zero,1,e16,mf4,ta,ma vle64.v v1,0(a0) vfmv.s.f v2,fa0 vsetvli zero,zero,e64,m1,ta,ma vadd.vv v1,v1,v1 zve64d: foo: vsetivli zero,1,e64,m1,ta,ma vle64.v v1,0(a0) vfmv.s.f v2,fa0 vadd.vv v1,v1,v1 PR target111037 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function. (second_sew_less_than_first_sew_p): Fix bug. (first_sew_less_than_second_sew_p): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111037-1.c: New test. * gcc.target/riscv/rvv/base/pr111037-2.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 22 +++++++++++++++++-- .../gcc.target/riscv/rvv/base/pr111037-1.c | 15 +++++++++++++ .../gcc.target/riscv/rvv/base/pr111037-2.c | 8 +++++++ 3 files changed, 43 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 08c487d82c0..79cbac01047 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1183,18 +1183,36 @@ second_ratio_invalid_for_first_lmul_p (const vector_insn_info &info1, return calculate_sew (info1.get_vlmul (), info2.get_ratio ()) == 0; } +static bool +float_insn_valid_sew_p (const vector_insn_info &info, unsigned int sew) +{ + if (info.get_insn () && info.get_insn ()->is_real () + && get_attr_type (info.get_insn ()->rtl ()) == TYPE_VFMOVFV) + { + if (sew == 16) + return TARGET_VECTOR_ELEN_FP_16; + else if (sew == 32) + return TARGET_VECTOR_ELEN_FP_32; + else if (sew == 64) + return TARGET_VECTOR_ELEN_FP_64; + } + return true; +} + static bool second_sew_less_than_first_sew_p (const vector_insn_info &info1, const vector_insn_info &info2) { - return info2.get_sew () < info1.get_sew (); + return info2.get_sew () < info1.get_sew () + || !float_insn_valid_sew_p (info1, info2.get_sew ()); } static bool first_sew_less_than_second_sew_p (const vector_insn_info &info1, const vector_insn_info &info2) { - return info1.get_sew () < info2.get_sew (); + return info1.get_sew () < info2.get_sew () + || !float_insn_valid_sew_p (info2, info1.get_sew ()); } /* return 0 if LMUL1 == LMUL2. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c new file mode 100644 index 00000000000..0b7b32fc3e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ + +#include "riscv_vector.h" + +void foo(_Float16 y, int64_t *i64p) +{ + vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1); + vx = __riscv_vadd_vv_i64m1 (vx, vx, 1); + vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1); + asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy)); +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c new file mode 100644 index 00000000000..ac50da71726 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */ + +#include "pr111037-1.c" + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */