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[8.43.85.97]) by mx.google.com with ESMTPS id kq1-20020a170906abc100b00997e71d0377si123510ejb.366.2023.08.17.12.26.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Aug 2023 12:26:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=fkfW23D7; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7325E3854826 for ; Thu, 17 Aug 2023 19:26:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7325E3854826 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692300415; bh=NKqvinlpXsqmg7sVlPwisIOyEZ8FifREyBdwjg7wqeo=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=fkfW23D7EwkvVuvum9SpzOb8D6YI0auhcD1/N0q+LVLfsevP437I7EWlkSbg0iuuA vR2ueD9VTHDm0+LElt60LuvWgMibccln3ShccF2fuf8ahxmTU+oId8fP6jiQZhhvQi pFZxBtlDSRa/hwZEG8Aud82ED0JQ9MAH4hawX1A0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id DC8283858D35 for ; Thu, 17 Aug 2023 19:26:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC8283858D35 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37HGhqD3027188 for ; Thu, 17 Aug 2023 12:26:10 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3shh34hys4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 17 Aug 2023 12:26:10 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 17 Aug 2023 12:26:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 17 Aug 2023 12:26:09 -0700 Received: from vpnclient.wrightpinski.org.com (unknown [10.69.242.187]) by maili.marvell.com (Postfix) with ESMTP id AEA9E3F707D; Thu, 17 Aug 2023 12:26:08 -0700 (PDT) To: CC: Andrew Pinski Subject: [PATCH] Document cond_neg, cond_one_cmpl, cond_len_neg and cond_len_one_cmpl standard patterns Date: Thu, 17 Aug 2023 12:25:54 -0700 Message-ID: <20230817192554.3137209-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-GUID: -fQ9snTeKKEn5TH_qxP-9VqWw7Qa8jjq X-Proofpoint-ORIG-GUID: -fQ9snTeKKEn5TH_qxP-9VqWw7Qa8jjq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-17_15,2023-08-17_02,2023-05-22_02 X-Spam-Status: No, score=-14.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Pinski via Gcc-patches From: Andrew Pinski Reply-To: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774505601615042921 X-GMAIL-MSGID: 1774505601615042921 When I added `cond_one_cmpl` (and the corresponding IFN) I had noticed cond_neg standard named pattern was not documented and this adds the documentation for all 4 named patterns now. OK? Tested by building the manual. gcc/ChangeLog: * doc/md.texi (Standard patterns): Document cond_neg, cond_one_cmpl, cond_len_neg and cond_len_one_cmpl. --- gcc/doc/md.texi | 62 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 70590e68ffe..89562fdb43c 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -7194,6 +7194,40 @@ move operand 2 or (operands 2 + operand 3) into operand 0 according to the comparison in operand 1. If the comparison is false, operand 2 is moved into operand 0, otherwise (operand 2 + operand 3) is moved. +@cindex @code{cond_neg@var{mode}} instruction pattern +@cindex @code{cond_one_cmpl@var{mode}} instruction pattern +@item @samp{cond_neg@var{mode}} +@itemx @samp{cond_one_cmpl@var{mode}} +When operand 1 is true, perform an operation on operands 2 and +store the result in operand 0, otherwise store operand 3 in operand 0. +The operation works elementwise if the operands are vectors. + +The scalar case is equivalent to: + +@smallexample +op0 = op1 ? @var{op} op2 : op3; +@end smallexample + +while the vector case is equivalent to: + +@smallexample +for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++) + op0[i] = op1[i] ? @var{op} op2[i] : op3[i]; +@end smallexample + +where, for example, @var{op} is @code{~} for @samp{cond_one_cmpl@var{mode}}. + +When defined for floating-point modes, the contents of @samp{op2[i]} +are not interpreted if @samp{op1[i]} is false, just like they would not +be in a normal C @samp{?:} condition. + +Operands 0, 2, and 3 all have mode @var{m}. Operand 1 is a scalar +integer if @var{m} is scalar, otherwise it has the mode returned by +@code{TARGET_VECTORIZE_GET_MASK_MODE}. + +@samp{cond_@var{op}@var{mode}} generally corresponds to a conditional +form of @samp{@var{op}@var{mode}2}. + @cindex @code{cond_add@var{mode}} instruction pattern @cindex @code{cond_sub@var{mode}} instruction pattern @cindex @code{cond_mul@var{mode}} instruction pattern @@ -7281,6 +7315,34 @@ for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++) op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i]; @end smallexample +@cindex @code{cond_len_neg@var{mode}} instruction pattern +@cindex @code{cond_len_one_cmpl@var{mode}} instruction pattern +@item @samp{cond_len_neg@var{mode}} +@itemx @samp{cond_len_one_cmpl@var{mode}} +When operand 1 is true and element index < operand 4 + operand 5, perform an operation on operands 1 and +store the result in operand 0, otherwise store operand 2 in operand 0. +The operation only works for the operands are vectors. + +@smallexample +for (i = 0; i < ops[4] + ops[5]; i++) + op0[i] = op1[i] ? @var{op} op2[i] : op3[i]; +@end smallexample + +where, for example, @var{op} is @code{~} for @samp{cond_len_one_cmpl@var{mode}}. + +When defined for floating-point modes, the contents of @samp{op2[i]} +are not interpreted if @samp{op1[i]} is false, just like they would not +be in a normal C @samp{?:} condition. + +Operands 0, 2, and 3 all have mode @var{m}. Operand 1 is a scalar +integer if @var{m} is scalar, otherwise it has the mode returned by +@code{TARGET_VECTORIZE_GET_MASK_MODE}. Operand 4 has whichever +integer mode the target prefers. + +@samp{cond_len_@var{op}@var{mode}} generally corresponds to a conditional +form of @samp{@var{op}@var{mode}2}. + + @cindex @code{cond_len_add@var{mode}} instruction pattern @cindex @code{cond_len_sub@var{mode}} instruction pattern @cindex @code{cond_len_mul@var{mode}} instruction pattern