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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id gt16-20020a170906f21000b00992f7e90360si11786881ejb.727.2023.08.17.00.27.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Aug 2023 00:27:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ppUUT8aD; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8ED3C3858C2C for ; Thu, 17 Aug 2023 07:27:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8ED3C3858C2C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692257223; bh=yicveuTVIMxi9A2rDXDBVQtlubGTzmIxdxs93gPDFxE=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=ppUUT8aDT0KZ00JbfLjKRtBdwDKlL0AdjZPpsgHTdPouQzbhznWmazQSoKLdgabrJ q9V7XVrc0ZdwiiFziROKswYEY6u8JFjY43l2bEA3PKCFbFr7Jz49zHy+7PtQeUUNHf Czh4YRLyIxsNpg0SWF22Lydo9OpHEBbyLrLfPhAU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id A1DEE3858D38 for ; Thu, 17 Aug 2023 07:26:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A1DEE3858D38 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="357701970" X-IronPort-AV: E=Sophos;i="6.01,179,1684825200"; d="scan'208";a="357701970" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2023 00:26:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="799916120" X-IronPort-AV: E=Sophos;i="6.01,179,1684825200"; d="scan'208";a="799916120" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga008.fm.intel.com with ESMTP; 17 Aug 2023 00:26:13 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id B52021006F3F; Thu, 17 Aug 2023 15:26:12 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFWREDOSUM.VS rounding mode intrinsic API Date: Thu, 17 Aug 2023 15:26:12 +0800 Message-Id: <20230817072612.4026035-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774460311679212052 X-GMAIL-MSGID: 1774460311679212052 From: Pan Li This patch would like to support the rounding mode API for the VFWREDOSUM.VS as the below samples * __riscv_vfwredosum_vs_f32m1_f64m1_rm * __riscv_vfwredosum_vs_f32m1_f64m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (widen_freducop): Add frm_opt_type template arg. (vfwredosum_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwredosum_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wredosum.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 9 ++++- .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 ++ .../riscv/rvv/base/float-point-wredosum.c | 33 +++++++++++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index ef2991359da..abf03bab0da 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1866,10 +1866,15 @@ public: }; /* Implements widening floating-point reduction instructions. */ -template +template class widen_freducop : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + bool apply_mask_policy_p () const override { return false; } rtx expand (function_expander &e) const override @@ -2544,6 +2549,7 @@ static CONSTEXPR const reducop vfredmax_obj; static CONSTEXPR const reducop vfredmin_obj; static CONSTEXPR const widen_freducop vfwredusum_obj; static CONSTEXPR const widen_freducop vfwredosum_obj; +static CONSTEXPR const widen_freducop vfwredosum_frm_obj; static CONSTEXPR const vmv vmv_x_obj; static CONSTEXPR const vmv_s vmv_s_obj; static CONSTEXPR const vmv vfmv_f_obj; @@ -2802,6 +2808,7 @@ BASE (vfredosum_frm) BASE (vfredmax) BASE (vfredmin) BASE (vfwredosum) +BASE (vfwredosum_frm) BASE (vfwredusum) BASE (vmv_x) BASE (vmv_s) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index da8412b66df..c1bb164a712 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -245,6 +245,7 @@ extern const function_base *const vfredosum_frm; extern const function_base *const vfredmax; extern const function_base *const vfredmin; extern const function_base *const vfwredosum; +extern const function_base *const vfwredosum_frm; extern const function_base *const vfwredusum; extern const function_base *const vmv_x; extern const function_base *const vmv_s; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 80e65bfb14b..da1157f5a56 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -507,6 +507,8 @@ DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops) DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops) DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops) +DEF_RVV_FUNCTION (vfwredosum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops) + /* 15. Vector Mask Instructions. */ // 15.1. Vector Mask-Register Logical Instructions diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c new file mode 100644 index 00000000000..acf79569a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat64m1_t +test_riscv_vfwredosum_vs_f32m1_f64m1_rm (vfloat32m1_t op1, vfloat64m1_t op2, + size_t vl) { + return __riscv_vfwredosum_vs_f32m1_f64m1_rm (op1, op2, 0, vl); +} + +vfloat64m1_t +test_vfwredosum_vs_f32m1_f64m1_rm_m (vbool32_t mask, vfloat32m1_t op1, + vfloat64m1_t op2, size_t vl) { + return __riscv_vfwredosum_vs_f32m1_f64m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m1_t +test_riscv_vfwredosum_vs_f32m1_f64m1 (vfloat32m1_t op1, vfloat64m1_t op2, + size_t vl) { + return __riscv_vfwredosum_vs_f32m1_f64m1 (op1, op2, vl); +} + +vfloat64m1_t +test_vfwredosum_vs_f32m1_f64m1_m (vbool32_t mask, vfloat32m1_t op1, + vfloat64m1_t op2, size_t vl) { + return __riscv_vfwredosum_vs_f32m1_f64m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */