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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id fy22-20020a170906b7d600b00982c06b45d9si10168067ejb.816.2023.08.16.01.42.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Aug 2023 01:42:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=s6OuasL1; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C85983858005 for ; Wed, 16 Aug 2023 08:42:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C85983858005 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692175325; bh=VO6xZmI7QIhJIPoWIvhH4wO0he0K3lE4ohg4j8ZpTUA=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=s6OuasL1cTj9s916s8U7MApweMubvYmmGmaXqYTJkW4Zt0QYhUmG+6jTaWlO4j1cs WoZX9qp8hRd5ewQDstmBRB+3du6SVPrwoDw0a8vHjXI5lzzBNzyXJ4FXLvbzv0woLF bsdgEACwFScRu7PaF03jzSrlRASmq87Esal8jeNI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 5CD923858C41 for ; Wed, 16 Aug 2023 08:41:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5CD923858C41 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="376205783" X-IronPort-AV: E=Sophos;i="6.01,176,1684825200"; d="scan'208";a="376205783" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2023 01:41:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="907938560" X-IronPort-AV: E=Sophos;i="6.01,176,1684825200"; d="scan'208";a="907938560" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga005.jf.intel.com with ESMTP; 16 Aug 2023 01:41:16 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.159.126]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A8A8B10080F8; Wed, 16 Aug 2023 16:41:15 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Support simplify (-1-x) for vector. Date: Wed, 16 Aug 2023 16:40:38 +0800 Message-ID: <20230816084038.2725233-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "yanzhang.wang--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: yanzhang.wang@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774374435587687378 X-GMAIL-MSGID: 1774374435587687378 From: Yanzhang Wang The pattern is enabled for scalar but not for vector. The patch try to make it consistent and will convert below code, shortcut_for_riscv_vrsub_case_1_32: vl1re32.v v1,0(a1) vsetvli zero,a2,e32,m1,ta,ma vrsub.vi v1,v1,-1 vs1r.v v1,0(a0) ret to, shortcut_for_riscv_vrsub_case_1_32: vl1re32.v v1,0(a1) vsetvli zero,a2,e32,m1,ta,ma vnot.v v1,v1 vs1r.v v1,0(a0) ret gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Get -1 with mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/simplify-vrsub.c: New test. Signed-off-by: Yanzhang Wang --- gcc/simplify-rtx.cc | 2 +- .../gcc.target/riscv/rvv/base/simplify-vrsub.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index d7315d82aa3..eb1ac120832 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -3071,7 +3071,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, /* (-1 - a) is ~a, unless the expression contains symbolic constants, in which case not retaining additions and subtractions could cause invalid assembly to be produced. */ - if (trueop0 == constm1_rtx + if (trueop0 == CONSTM1_RTX (mode) && !contains_symbolic_reference_p (op1)) return simplify_gen_unary (NOT, mode, op1, mode); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c new file mode 100644 index 00000000000..df87ed94ea4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +#define VRSUB_WITH_LMUL(LMUL, DTYPE) \ + vint##DTYPE##m##LMUL##_t \ + shortcut_for_riscv_vrsub_case_##LMUL##_##DTYPE \ + (vint##DTYPE##m##LMUL##_t v1, \ + size_t vl) \ + { \ + return __riscv_vrsub_vx_i##DTYPE##m##LMUL (v1, -1, vl); \ + } + +VRSUB_WITH_LMUL (1, 16) +VRSUB_WITH_LMUL (1, 32) + +/* { dg-final { scan-assembler-times {vnot\.v} 2 } } */