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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m16-20020a17090679d000b0099ce23c3a71si8939714ejo.1041.2023.08.14.22.02.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Aug 2023 22:02:43 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="Ura/Qhzt"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 882DC3857030 for ; Tue, 15 Aug 2023 05:02:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 882DC3857030 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692075759; bh=yUPGsstW2r27oBklJr+yNjQJtZcOo4hvoph86e2igYM=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Ura/QhztaVavTvuZrKBfxEMFmWqrAfnNxcvp73RT3j1BfQbxPhszzH1QgTK5oGD/X D8TquXs+Ij2/fv41a1qWjmpM1e1yfb7Qkyq0t7YAKgF96oWWM02a490IfgY/Js3If2 1vwO8d7LQOxaFojKegmInvsx2qc/LFnfl/fwEBW4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 3309A3858422 for ; Tue, 15 Aug 2023 05:01:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3309A3858422 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="375932490" X-IronPort-AV: E=Sophos;i="6.01,173,1684825200"; d="scan'208";a="375932490" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 22:01:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="803686503" X-IronPort-AV: E=Sophos;i="6.01,173,1684825200"; d="scan'208";a="803686503" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 14 Aug 2023 22:01:50 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 17D19100518B; Tue, 15 Aug 2023 13:01:49 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFCVT.XU.F.V rounding mode intrinsic API Date: Tue, 15 Aug 2023 13:01:46 +0800 Message-Id: <20230815050146.204188-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774270035692289115 X-GMAIL-MSGID: 1774270035692289115 From: Pan Li This patch would like to support the rounding mode API for the VFCVT.XU.F.V as the below samples. * __riscv_vfcvt_xu_f_v_u32m1_rm * __riscv_vfcvt_xu_f_v_u32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (vfcvt_xu_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfcvt_xu_frm): New intrinsic function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cvt-xu.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 2 ++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 1 + .../riscv/rvv/base/float-point-cvt-xu.c | 29 +++++++++++++++++++ 4 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 754a53efd3d..8eb89a05580 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2482,6 +2482,7 @@ static CONSTEXPR const vmv_v vfmv_v_obj; static CONSTEXPR const vfcvt_x vfcvt_x_obj; static CONSTEXPR const vfcvt_x_frm vfcvt_x_frm_obj; static CONSTEXPR const vfcvt_x vfcvt_xu_obj; +static CONSTEXPR const vfcvt_x_frm vfcvt_xu_frm_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj; static CONSTEXPR const vfcvt_f vfcvt_f_obj; @@ -2732,6 +2733,7 @@ BASE (vfmv_v) BASE (vfcvt_x) BASE (vfcvt_x_frm) BASE (vfcvt_xu) +BASE (vfcvt_xu_frm) BASE (vfcvt_rtz_x) BASE (vfcvt_rtz_xu) BASE (vfcvt_f) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 50a7d7ffb6f..98b61655692 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -207,6 +207,7 @@ extern const function_base *const vfmv_v; extern const function_base *const vfcvt_x; extern const function_base *const vfcvt_x_frm; extern const function_base *const vfcvt_xu; +extern const function_base *const vfcvt_xu_frm; extern const function_base *const vfcvt_rtz_x; extern const function_base *const vfcvt_rtz_xu; extern const function_base *const vfcvt_f; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 8b6a7cc49f3..613bbe7a855 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -446,6 +446,7 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops) DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops) DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops) +DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops) // 13.18. Widening Floating-Point/Integer Type-Convert Instructions DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c new file mode 100644 index 00000000000..bb164b2b001 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint32m1_t +test_riscv_vfcvt_xu_f_v_u32m1_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m1_rm (op1, 0, vl); +} + +vuint32m1_t +test_vfcvt_xu_f_v_u32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m1_rm_m (mask, op1, 1, vl); +} + +vuint32m1_t +test_riscv_vfcvt_xu_f_vv_u32m1 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m1 (op1, vl); +} + +vuint32m1_t +test_vfcvt_xu_f_v_u32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */