diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index b13ff53d36f..fb003bcd67b 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -917,6 +917,7 @@
 
 (define_int_attr mve_insn [
 		 (UNSPEC_VCADD90 "vcadd") (UNSPEC_VCADD270 "vcadd")
+		 (UNSPEC_VCMLA "vcmla") (UNSPEC_VCMLA90 "vcmla") (UNSPEC_VCMLA180 "vcmla") (UNSPEC_VCMLA270 "vcmla")
 		 (UNSPEC_VCMUL "vcmul") (UNSPEC_VCMUL90 "vcmul") (UNSPEC_VCMUL180 "vcmul") (UNSPEC_VCMUL270 "vcmul")
 		 (VABAVQ_P_S "vabav") (VABAVQ_P_U "vabav")
 		 (VABAVQ_S "vabav") (VABAVQ_U "vabav")
@@ -1044,6 +1045,13 @@
 		 (VMOVNTQ_S "vmovnt") (VMOVNTQ_U "vmovnt")
 		 (VMULHQ_M_S "vmulh") (VMULHQ_M_U "vmulh")
 		 (VMULHQ_S "vmulh") (VMULHQ_U "vmulh")
+		 (VMULLBQ_INT_M_S "vmullb") (VMULLBQ_INT_M_U "vmullb")
+		 (VMULLBQ_INT_S "vmullb") (VMULLBQ_INT_U "vmullb")
+		 (VMULLBQ_POLY_M_P "vmullb") (VMULLTQ_POLY_M_P "vmullt")
+		 (VMULLBQ_POLY_P "vmullb")
+		 (VMULLTQ_INT_M_S "vmullt") (VMULLTQ_INT_M_U "vmullt")
+		 (VMULLTQ_INT_S "vmullt") (VMULLTQ_INT_U "vmullt")
+		 (VMULLTQ_POLY_P "vmullt")
 		 (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul")
 		 (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul")
 		 (VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F "vmul")
@@ -1209,7 +1217,6 @@
 		 (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
 		 (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
 		 (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
-		 (UNSPEC_VCMLA "vcmla") (UNSPEC_VCMLA90 "vcmla") (UNSPEC_VCMLA180 "vcmla") (UNSPEC_VCMLA270 "vcmla")
 		 ])
 
 (define_int_attr isu    [
@@ -1246,6 +1253,8 @@
 		 (VMOVNBQ_S "i") (VMOVNBQ_U "i")
 		 (VMOVNTQ_M_S "i") (VMOVNTQ_M_U "i")
 		 (VMOVNTQ_S "i") (VMOVNTQ_U "i")
+		 (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u")
+		 (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u")
 		 (VNEGQ_M_S "s")
 		 (VQABSQ_M_S "s")
 		 (VQMOVNBQ_M_S "s") (VQMOVNBQ_M_U "u")
@@ -2330,6 +2339,10 @@
 		       (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
 		       (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
 		       (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
+		       (VMULLBQ_POLY_P "p")
+		       (VMULLTQ_POLY_P "p")
+		       (VMULLBQ_POLY_M_P "p")
+		       (VMULLTQ_POLY_M_P "p")
 		       (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
 		       (VMULQ_U "u")
 		       (VQADDQ_N_S "s") (VQADDQ_N_U "u")
@@ -2713,8 +2726,8 @@
 (define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
 (define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
 (define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
-(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
-(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
+(define_int_iterator VMULLxQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S VMULLTQ_INT_U VMULLTQ_INT_S])
+(define_int_iterator VMULLxQ_POLY [VMULLBQ_POLY_P VMULLTQ_POLY_P])
 (define_int_iterator VMULQ [VMULQ_U VMULQ_S])
 (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
 (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
@@ -2815,7 +2828,8 @@
 (define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
 (define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
 (define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
-(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
+(define_int_iterator VMULLxQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S VMULLTQ_INT_M_U VMULLTQ_INT_M_S])
+(define_int_iterator VMULLxQ_POLY_M [VMULLBQ_POLY_M_P VMULLTQ_POLY_M_P])
 (define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
 (define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
 (define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
@@ -2844,7 +2858,6 @@
 (define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
 (define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
 (define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
-(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
 (define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
 (define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
 (define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index a2cbcff1a6f..2001e95a5f1 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -976,32 +976,18 @@
 ])
 
 ;;
-;; [vmullbq_int_u, vmullbq_int_s])
+;; [vmullbq_int_u, vmullbq_int_s]
+;; [vmulltq_int_u, vmulltq_int_s]
 ;;
-(define_insn "mve_vmullbq_int_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_int_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
 	(unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
 				  (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMULLBQ_INT))
+	 VMULLxQ_INT))
   ]
   "TARGET_HAVE_MVE"
-  "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmulltq_int_u, vmulltq_int_s])
-;;
-(define_insn "mve_vmulltq_int_<supf><mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
-	(unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
-				  (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMULLTQ_INT))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
+  "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1528,32 +1514,18 @@
 ])
 
 ;;
-;; [vmulltq_poly_p])
-;;
-(define_insn "mve_vmulltq_poly_p<mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
-	(unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
-				  (match_operand:MVE_3 2 "s_register_operand" "w")]
-	 VMULLTQ_POLY_P))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmullbq_poly_p])
+;; [vmulltq_poly_p]
+;; [vmullbq_poly_p]
 ;;
-(define_insn "mve_vmullbq_poly_p<mode>"
+(define_insn "@mve_<mve_insn>q_poly_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
 	(unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
 				  (match_operand:MVE_3 2 "s_register_operand" "w")]
-	 VMULLBQ_POLY_P))
+	 VMULLxQ_POLY))
   ]
   "TARGET_HAVE_MVE"
-  "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
+  "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2816,36 +2788,20 @@
    (set_attr "length""8")])
 
 ;;
-;; [vmullbq_int_m_u, vmullbq_int_m_s])
+;; [vmullbq_int_m_u, vmullbq_int_m_s]
+;; [vmulltq_int_m_s, vmulltq_int_m_u]
 ;;
-(define_insn "mve_vmullbq_int_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_int_m_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
 	(unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
 				  (match_operand:MVE_2 2 "s_register_operand" "w")
 				  (match_operand:MVE_2 3 "s_register_operand" "w")
 				  (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-	 VMULLBQ_INT_M))
+	 VMULLxQ_INT_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmullbt.<supf>%#<V_sz_elem>	%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vmulltq_int_m_s, vmulltq_int_m_u])
-;;
-(define_insn "mve_vmulltq_int_m_<supf><mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
-	(unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
-				  (match_operand:MVE_2 2 "s_register_operand" "w")
-				  (match_operand:MVE_2 3 "s_register_operand" "w")
-				  (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-	 VMULLTQ_INT_M))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vmulltt.<supf>%#<V_sz_elem>	%q0, %q2, %q3"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3006,36 +2962,20 @@
    (set_attr "length""8")])
 
 ;;
-;; [vmullbq_poly_m_p])
+;; [vmullbq_poly_m_p]
+;; [vmulltq_poly_m_p]
 ;;
-(define_insn "mve_vmullbq_poly_m_p<mode>"
+(define_insn "@mve_<mve_insn>q_poly_m_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
 	(unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
 		       (match_operand:MVE_3 2 "s_register_operand" "w")
 		       (match_operand:MVE_3 3 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-	 VMULLBQ_POLY_M_P))
+	 VMULLxQ_POLY_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vmulltq_poly_m_p])
-;;
-(define_insn "mve_vmulltq_poly_m_p<mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
-	(unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
-		       (match_operand:MVE_3 2 "s_register_operand" "w")
-		       (match_operand:MVE_3 3 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-	 VMULLTQ_POLY_M_P))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
