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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d26-20020a05640208da00b00523405ffb8bsi7462077edz.422.2023.08.13.19.37.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Aug 2023 19:37:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=b6MFOu1i; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9DA863858C3A for ; Mon, 14 Aug 2023 02:37:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9DA863858C3A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691980635; bh=Ti2GtxVPVyoMvuzEK7Ddc/8HezhMOMOlAB36zhNXO1w=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=b6MFOu1iMRqdPVi5oXf2hc6YP5XbTxGbhlfEA+LBxan2q1uuyU0Ka1DF993oDpNH5 kpfLPltxZ6ByiJKe82wIz/fb+hWDQAqLgNr/WuJ6CoYXHBbLhMX2PdguFob35GkvnL BM4srPbiFzgBSssDE9pYo9lpl0OoBau8l3jOWnTE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 795F43858D39 for ; Mon, 14 Aug 2023 02:36:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 795F43858D39 X-IronPort-AV: E=McAfee;i="6600,9927,10801"; a="369418678" X-IronPort-AV: E=Sophos;i="6.01,171,1684825200"; d="scan'208";a="369418678" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2023 19:36:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10801"; a="907071862" X-IronPort-AV: E=Sophos;i="6.01,171,1684825200"; d="scan'208";a="907071862" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 13 Aug 2023 19:36:27 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id D5C60100516E; Mon, 14 Aug 2023 10:36:26 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFWNMACC rounding mode intrinsic API Date: Mon, 14 Aug 2023 10:36:25 +0800 Message-Id: <20230814023625.1355161-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774170288336857103 X-GMAIL-MSGID: 1774170288336857103 From: Pan Li This patch would like to support the rounding mode API for the VFWNMACC as the below samples. * __riscv_vfwnmacc_vv_f64m2_rm * __riscv_vfwnmacc_vv_f64m2_rm_m * __riscv_vfwnmacc_vf_f64m2_rm * __riscv_vfwnmacc_vf_f64m2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfwnmacc_frm): New class for frm. (vfwnmacc_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwnmacc_frm): New intrinsic function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wnmacc.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-wnmacc.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index e84d6d1d047..4a7f2b8e3e9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -562,6 +562,29 @@ public: } }; +/* Implements below instructions for frm + - vfwnmacc +*/ +class vfwnmacc_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg_scalar (MINUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg (MINUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2340,6 +2363,7 @@ static CONSTEXPR const vfmsub_frm vfmsub_frm_obj; static CONSTEXPR const vfwmacc vfwmacc_obj; static CONSTEXPR const vfwmacc_frm vfwmacc_frm_obj; static CONSTEXPR const vfwnmacc vfwnmacc_obj; +static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; static CONSTEXPR const vfwnmsac vfwnmsac_obj; static CONSTEXPR const unop vfsqrt_obj; @@ -2584,6 +2608,7 @@ BASE (vfmsub_frm) BASE (vfwmacc) BASE (vfwmacc_frm) BASE (vfwnmacc) +BASE (vfwnmacc_frm) BASE (vfwmsac) BASE (vfwnmsac) BASE (vfsqrt) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index acbc7d42fbe..27c7deb4ec2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -178,6 +178,7 @@ extern const function_base *const vfmsub_frm; extern const function_base *const vfwmacc; extern const function_base *const vfwmacc_frm; extern const function_base *const vfwnmacc; +extern const function_base *const vfwnmacc_frm; extern const function_base *const vfwmsac; extern const function_base *const vfwnmsac; extern const function_base *const vfsqrt; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 0b73a5bcbc5..481c3b899f2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -378,6 +378,8 @@ DEF_RVV_FUNCTION (vfwnmsac, alu, full_preds, f_wwfv_ops) DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwvv_ops) DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwfv_ops) +DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwvv_ops) +DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwfv_ops) // 13.8. Vector Floating-Point Square-Root Instruction DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c new file mode 100644 index 00000000000..2602289ec88 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwnmacc_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmacc_vv_f64m2_rm (vd, op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmacc_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwnmacc_vf_f32m1_rm (vfloat64m2_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmacc_vf_f64m2_rm (vd, op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwnmacc_vf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmacc_vf_f64m2_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwnmacc_vv_f32m1 (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmacc_vv_f64m2 (vd, op1, op2, vl); +} + +vfloat64m2_t +test_vfwnmacc_vv_f32m1_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmacc_vv_f64m2_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwnmacc\.[vw][vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */