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[8.43.85.97]) by mx.google.com with ESMTPS id o6-20020a170906358600b0099b921de2fasi2673549ejb.964.2023.08.10.19.29.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Aug 2023 19:29:10 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=etfqvQS5; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 678E73858426 for ; Fri, 11 Aug 2023 02:29:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 678E73858426 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691720949; bh=6YporwLsb72EuQ7/93kozWb+soOjCcNQKfO8vaYkdSE=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=etfqvQS5B6zlx63CP+oH5IXMcA1AE0EDqrCyxeMmhxI8CHTDjvM+Dw5aMtAGbTVle UqOAw0gHdPCV4Y+wTSzf+QfS9DxCOD+GiNLElIsN6Dm1meiqj8HWNx9ZEJftRY/Xpq qxG/agFJwXSUi+coH7cXCiF3CTv9NHoBAk9XqzRY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id B64463858D20 for ; Fri, 11 Aug 2023 02:28:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B64463858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="371580869" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="371580869" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 19:28:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="735622583" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="735622583" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga007.fm.intel.com with ESMTP; 10 Aug 2023 19:28:21 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id DDB6010054E6; Fri, 11 Aug 2023 10:28:20 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFMSAC rounding mode intrinsic API Date: Fri, 11 Aug 2023 10:28:19 +0800 Message-Id: <20230811022819.1113702-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773897987617547022 X-GMAIL-MSGID: 1773897987617547022 From: Pan Li This patch would like to support the rounding mode API for the VFMSAC for the below samples. * __riscv_vfmsac_vv_f32m1_rm * __riscv_vfmsac_vv_f32m1_rm_m * __riscv_vfmsac_vf_f32m1_rm * __riscv_vfmsac_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: (class vfmsac_frm): New class for vfmsac frm. (vfmsac_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmsac_frm): New function definition gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-msac.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-msac.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 1d4a5a18bf9..8d3970b28db 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -401,6 +401,29 @@ public: } }; +/* Implements below instructions for frm + - vfmsac +*/ +class vfmsac_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn ( + true, code_for_pred_mul_scalar (MINUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn ( + true, code_for_pred_mul (MINUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2168,6 +2191,7 @@ static CONSTEXPR const vfnmsub vfnmsub_obj; static CONSTEXPR const vfnmacc vfnmacc_obj; static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj; static CONSTEXPR const vfmsac vfmsac_obj; +static CONSTEXPR const vfmsac_frm vfmsac_frm_obj; static CONSTEXPR const vfnmadd vfnmadd_obj; static CONSTEXPR const vfmsub vfmsub_obj; static CONSTEXPR const vfwmacc vfwmacc_obj; @@ -2405,6 +2429,7 @@ BASE (vfnmsub) BASE (vfnmacc) BASE (vfnmacc_frm) BASE (vfmsac) +BASE (vfmsac_frm) BASE (vfnmadd) BASE (vfmsub) BASE (vfwmacc) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 247074d0868..ca8a6dc1cc3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -167,6 +167,7 @@ extern const function_base *const vfnmsub; extern const function_base *const vfnmacc; extern const function_base *const vfnmacc_frm; extern const function_base *const vfmsac; +extern const function_base *const vfmsac_frm; extern const function_base *const vfnmadd; extern const function_base *const vfmsub; extern const function_base *const vfwmacc; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 7aae0665520..51a14e49075 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -353,6 +353,8 @@ DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops) DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops) +DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvvv_ops) +DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops) // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c new file mode 100644 index 00000000000..8fee552dd30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsac_vv_f32m1_rm (vd, op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsac_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmsac_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmsac_vf_f32m1_rm (vd, op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmsac_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsac_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmsac_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsac_vv_f32m1 (vd, op1, op2, vl); +} + +vfloat32m1_t +test_vfmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsac_vv_f32m1_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmsac\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */