diff mbox series

RISC-V: Add MASK vec_duplicate pattern[PR110962]

Message ID 20230810103705.1697293-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add MASK vec_duplicate pattern[PR110962] |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Aug. 10, 2023, 10:37 a.m. UTC 
  This patch fix bug:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110962

SUBROUTINE a(b,c,d)
  LOGICAL,DIMENSION(INOUT)  :: b
  LOGICAL e
  REAL, DIMENSION(IN)     ::  c
  REAL, DIMENSION(INOUT)  ::  d
  REAL, DIMENSION(SIZE(c))   :: f
  WHERE (b.AND.e)
     WHERE (f>=0.)
        d = g
     ENDWHERE
  ENDWHERE
END SUBROUTINE a

   PR target/110962

gcc/ChangeLog:

        * config/riscv/autovec.md (vec_duplicate<mode>): New pattern.

---
 gcc/config/riscv/autovec.md | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Robin Dapp Aug. 10, 2023, 11:55 a.m. UTC | #1 
Is the testcase already in the test suite?  If not we should add it.
Apart from that LGTM. 

Regards
 Robin
juzhe.zhong@rivai.ai Aug. 10, 2023, 11:57 a.m. UTC | #2 
I didn't add it.... since I don't know how to add a target specific fortran testcase.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-08-10 19:55
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add MASK vec_duplicate pattern[PR110962]
Is the testcase already in the test suite?  If not we should add it.
Apart from that LGTM. 
 
Regards
Robin
juzhe.zhong@rivai.ai Aug. 10, 2023, 12:38 p.m. UTC | #3 
Is this patch ok ? Maybe we can find a way to add a target specific fortran test but should not block this bug fix.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-08-10 19:55
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add MASK vec_duplicate pattern[PR110962]
Is the testcase already in the test suite?  If not we should add it.
Apart from that LGTM. 
 
Regards
Robin
Robin Dapp Aug. 10, 2023, 12:45 p.m. UTC | #4 
> Is this patch ok ? Maybe we can find a way to add a target specific
> fortran test but should not block this bug fix.

It's not much different than adding a C testcase actually, apart from 
starting comments with a !

But well, LGTM.  The test doesn't look that complicated and quite likely
is covered by the Fortran testsuite already.

Regards
 Robin
Li, Pan2 via Gcc-patches Aug. 10, 2023, 1:19 p.m. UTC | #5 
Committed, thanks Robin.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Robin Dapp via Gcc-patches
Sent: Thursday, August 10, 2023 8:45 PM
To: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: rdapp.gcc@gmail.com; kito.cheng <kito.cheng@gmail.com>; Kito.cheng <kito.cheng@sifive.com>; jeffreyalaw <jeffreyalaw@gmail.com>
Subject: Re: [PATCH] RISC-V: Add MASK vec_duplicate pattern[PR110962]

> Is this patch ok ? Maybe we can find a way to add a target specific
> fortran test but should not block this bug fix.

It's not much different than adding a C testcase actually, apart from 
starting comments with a !

But well, LGTM.  The test doesn't look that complicated and quite likely
is covered by the Fortran testsuite already.

Regards
 Robin
diff mbox series

Patch

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 6cb5fa3ed27..3b396a9a990 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -287,6 +287,27 @@ 
 ;; == Vector creation
 ;; =========================================================================
 
+;; -------------------------------------------------------------------------
+;; ---- [BOOL] Duplicate element
+;; -------------------------------------------------------------------------
+;; The patterns in this section are synthetic.
+;; -------------------------------------------------------------------------
+
+;; Implement a predicate broadcast by shifting the low bit of the scalar
+;; input into the top bit by duplicate the input and do a compare with zero.
+(define_expand "vec_duplicate<mode>"
+  [(set (match_operand:VB 0 "register_operand")
+	(vec_duplicate:VB (match_operand:QI 1 "register_operand")))]
+  "TARGET_VECTOR"
+  {
+    poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode);
+    machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
+    rtx dup = expand_vector_broadcast (mode, operands[1]);
+    riscv_vector::expand_vec_cmp (operands[0], NE, dup, CONST0_RTX (mode));
+    DONE;
+  }
+)
+
 ;; -------------------------------------------------------------------------
 ;; ---- [INT] Linear series
 ;; -------------------------------------------------------------------------