diff mbox series

RISC-V: Support TU for integer ternary OP[PR110964]

Message ID 20230810092146.839668-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Support TU for integer ternary OP[PR110964] |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Aug. 10, 2023, 9:21 a.m. UTC 
  PR target/110964

gcc/ChangeLog:

        * config/riscv/riscv-v.cc (expand_cond_len_ternop): Add integer ternary.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/pr110964.c: New test.

---
 gcc/config/riscv/riscv-v.cc                         |  3 +--
 .../gcc.target/riscv/rvv/autovec/pr110964.c         | 13 +++++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c

Comments

Robin Dapp Aug. 10, 2023, 12:09 p.m. UTC | #1 
OK.

Regards
 Robin
Li, Pan2 via Gcc-patches Aug. 10, 2023, 12:23 p.m. UTC | #2 
Committed, thanks Robin.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Robin Dapp via Gcc-patches
Sent: Thursday, August 10, 2023 8:09 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; kito.cheng@gmail.com; kito.cheng@sifive.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH] RISC-V: Support TU for integer ternary OP[PR110964]

OK.

Regards
 Robin
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c9f0a4a9e7b..a3062c90618 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3604,8 +3604,7 @@  expand_cond_len_ternop (unsigned icode, rtx *ops)
       if (FLOAT_MODE_P (mode))
 	emit_nonvlmax_fp_ternary_tu_insn (icode, RVV_TERNOP_TU, ops, len);
       else
-	/* FIXME: Enable this case when we support it in the middle-end.  */
-	gcc_unreachable ();
+	emit_nonvlmax_tu_insn (icode, RVV_TERNOP_TU, ops, len);
     }
   else
     {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
new file mode 100644
index 00000000000..cf2d1fb5f1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */
+
+int *a;
+long b, c;
+
+int d ()
+{
+  const int e;
+  for (; a < e; a++) /* { dg-warning "comparison between pointer and integer" } */
+    c += *a * b;
+}
+