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(unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 42CCE4402F; Wed, 9 Aug 2023 11:53:58 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 06/14] LoongArch: Fix 64-bit immediate move for loongarch32 target Date: Wed, 9 Aug 2023 19:46:13 +0800 Message-ID: <20230809115325.3716347-7-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773752599816484125 X-GMAIL-MSGID: 1773752599816484125 loongarch_move_integer does not support splitting 64-bit integer into two 32-bit ones. Thus, define_split is removed from movdi_32bit and TARGET_64BIT is added to the split condition of movdi_64bit to avoid using it for loongarch32. gcc/ChangeLog: * config/loongarch/loongarch.md (movdi_32bit): Remove not working split, use existing loongarch_split_move instead. (movdi_64bit): Add TARGET_64BIT to split condition. --- gcc/config/loongarch/loongarch.md | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 9eb6bb75c35..c611a8a822a 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1777,22 +1777,13 @@ DONE; }) -(define_insn_and_split "*movdi_32bit" +(define_insn "*movdi_32bit" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,w,*f,*f,*r,*m") (match_operand:DI 1 "move_operand" "r,i,w,r,*J*r,*m,*f,*f"))] "!TARGET_64BIT && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return loongarch_output_move (operands[0], operands[1]); } - "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO - (operands[0]))" - [(const_int 0)] - " -{ - loongarch_move_integer (operands[0], operands[0], INTVAL (operands[1])); - DONE; -} - " [(set_attr "move_type" "move,const,load,store,mgtf,fpload,mftg,fpstore") (set_attr "mode" "DI")]) @@ -1804,7 +1795,7 @@ || reg_or_0_operand (operands[1], DImode))" { return loongarch_output_move (operands[0], operands[1]); } "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO - (operands[0]))" + (operands[0])) && TARGET_64BIT" [(const_int 0)] " {