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(unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 589C843FAD; Wed, 9 Aug 2023 11:53:56 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 05/14] LoongArch: Fix 64-bit move for loongarch32 target Date: Wed, 9 Aug 2023 19:46:12 +0800 Message-ID: <20230809115325.3716347-6-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773752427256915759 X-GMAIL-MSGID: 1773752427256915759 Bring back 64-bit move splitting for loongarch32. The code was removed in commit 16fc26d4e7a (`LoongArch: Support split symbol.`) for unknown reason. gcc/ChangeLog: * config/loongarch/loongarch.md: Handle move splitting for 64-bit operands. --- gcc/config/loongarch/loongarch.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 93d8bf5bcca..9eb6bb75c35 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1965,6 +1965,16 @@ [(set_attr "move_type" "move,load,store") (set_attr "mode" "DF")]) +(define_split + [(set (match_operand:MOVE64 0 "nonimmediate_operand") + (match_operand:MOVE64 1 "move_operand"))] + "reload_completed && loongarch_split_move_p (operands[0], operands[1])" + [(const_int 0)] +{ + loongarch_split_move (operands[0], operands[1], curr_insn); + DONE; +}) + ;; Emit a doubleword move in which exactly one of the operands is ;; a floating-point register. We can't just emit two normal moves ;; because of the constraints imposed by the FPU register model;