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(unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id CFFAD43FAD; Wed, 9 Aug 2023 11:54:07 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 11/14] LoongArch: Mark am* instructions as LA64-only Date: Wed, 9 Aug 2023 19:46:18 +0800 Message-ID: <20230809115325.3716347-12-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773752913038464532 X-GMAIL-MSGID: 1773752913038464532 LoongArch32 only provides basic ll/sc instructions for atomic operations. Mark am* atomic instructions as 64-bit only. gcc/ChangeLog: * config/loongarch.sync.md: Guard am* atomic insns by TARGET_64BIT. --- gcc/config/loongarch/sync.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index 9924d522bcd..151b553bcc6 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -77,7 +77,7 @@ [(match_operand:GPR 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] - "" + "TARGET_64BIT" "amswap%A2.\t$zero,%z1,%0" [(set (attr "length") (const_int 8))]) @@ -88,7 +88,7 @@ (match_operand:GPR 1 "reg_or_0_operand" "rJ")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "" + "TARGET_64BIT" "am%A2.\t$zero,%z1,%0" [(set (attr "length") (const_int 8))]) @@ -101,7 +101,7 @@ (match_operand:GPR 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "" + "TARGET_64BIT" "am%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 8))]) @@ -113,7 +113,7 @@ UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) (match_operand:GPR 2 "register_operand" "r"))] - "" + "TARGET_64BIT" "amswap%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 8))]) @@ -182,7 +182,7 @@ [(match_operand:QI 0 "register_operand" "") ;; bool output (match_operand:QI 1 "memory_operand" "+ZB") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "" + "TARGET_64BIT" { /* We have no QImode atomics, so use the address LSBs to form a mask, then use an aligned SImode atomic. */