diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 6cb5fa3ed27..7ddb05695fd 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -297,7 +297,7 @@
 ;; -------------------------------------------------------------------------
 
 (define_expand "@vec_series<mode>"
-  [(match_operand:VI 0 "register_operand")
+  [(match_operand:V_VLSI 0 "register_operand")
    (match_operand:<VEL> 1 "reg_or_int_operand")
    (match_operand:<VEL> 2 "reg_or_int_operand")]
   "TARGET_VECTOR"
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a91ddfcc150..d4b76dbe5e8 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1323,7 +1323,8 @@ expand_vec_series (rtx dest, rtx base, rtx step)
   rtx step_adj;
   if (rtx_equal_p (step, const1_rtx))
     step_adj = vid;
-  else if (rtx_equal_p (step, constm1_rtx) && poly_int_rtx_p (base, &value)
+  else if (rtx_equal_p (step, constm1_rtx)
+	   && poly_int_rtx_p (base, &value)
 	   && known_eq (nunits_m1, value))
     {
       /* Special case:
@@ -1333,9 +1334,20 @@ expand_vec_series (rtx dest, rtx base, rtx step)
 	 Code sequence:
 	   vid.v v
 	   vrsub nunits - 1, v.  */
-      rtx ops[] = {dest, vid, gen_int_mode (nunits_m1, GET_MODE_INNER (mode))};
-      insn_code icode = code_for_pred_sub_reverse_scalar (mode);
-      emit_vlmax_insn (icode, RVV_BINOP, ops);
+      if (value.is_constant () && IN_RANGE (value.to_constant (), -16, 15))
+	{
+	  rtx dup = gen_const_vector_dup (mode, value);
+	  rtx ops[] = {dest, dup, vid};
+	  insn_code icode = code_for_pred (MINUS, mode);
+	  emit_vlmax_insn (icode, RVV_BINOP, ops);
+	}
+      else
+	{
+	  rtx ops[]
+	    = {dest, vid, gen_int_mode (nunits_m1, GET_MODE_INNER (mode))};
+	  insn_code icode = code_for_pred_sub_reverse_scalar (mode);
+	  emit_vlmax_insn (icode, RVV_BINOP, ops);
+	}
       return;
     }
   else
@@ -1416,7 +1428,9 @@ expand_const_vector (rtx target, rtx src)
   rtx base, step;
   if (const_vec_series_p (src, &base, &step))
     {
-      emit_insn (gen_vec_series (mode, target, base, step));
+      rtx tmp = gen_reg_rtx (mode);
+      emit_insn (gen_vec_series (mode, tmp, base, step));
+      emit_move_insn (target, tmp);
       return;
     }
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f9b53d21d1b..3d3767bc563 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1335,7 +1335,7 @@ riscv_const_insns (rtx x)
 	       out range of [-16, 15].
 	  - 3. const series vector.
 	  ...etc.  */
-	if (riscv_v_ext_vector_mode_p (GET_MODE (x)))
+	if (riscv_v_ext_mode_p (GET_MODE (x)))
 	  {
 	    /* const series vector.  */
 	    rtx base, step;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 14829989e09..30808ceb241 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -468,6 +468,7 @@
   (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
   (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
 
+  (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
   (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
   (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
   (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
@@ -479,6 +480,7 @@
   (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
   (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
   (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
+  (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
   (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
   (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
   (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
@@ -489,6 +491,7 @@
   (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
   (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
   (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
+  (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
   (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
   (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
   (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 65b5fe456ed..a839d5f7667 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -5974,8 +5974,8 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_series<mode>"
-  [(set (match_operand:VI 0 "register_operand"           "=vd, vd, vr, vr")
-	(if_then_else:VI
+  [(set (match_operand:V_VLSI 0 "register_operand"           "=vd, vd, vr, vr")
+	(if_then_else:V_VLSI
 	  (unspec:<VM>
 	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
 	     (match_operand 3 "vector_length_operand"    " rK, rK, rK, rK")
@@ -5984,8 +5984,8 @@
 	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (vec_series:VI (const_int 0) (const_int 1))
-	  (match_operand:VI 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
+	  (vec_series:V_VLSI (const_int 0) (const_int 1))
+	  (match_operand:V_VLSI 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "vid.v\t%0%p1"
   [(set_attr "type" "vmidx")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
new file mode 100644
index 00000000000..f3217e6063e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_CONST (int16_t, -16, 2)
+DEF_CONST (int16_t, -16, 4)
+DEF_CONST (int16_t, -16, 8)
+DEF_CONST (int16_t, -16, 16)
+DEF_CONST (int16_t, -16, 32)
+DEF_CONST (int16_t, -16, 64)
+DEF_CONST (int16_t, -16, 128)
+DEF_CONST (int16_t, -16, 256)
+DEF_CONST (int16_t, -16, 512)
+DEF_CONST (int16_t, -16, 1024)
+DEF_CONST (int16_t, -16, 2048)
+
+DEF_CONST (int32_t, -16, 2)
+DEF_CONST (int32_t, -16, 4)
+DEF_CONST (int32_t, -16, 8)
+DEF_CONST (int32_t, -16, 16)
+DEF_CONST (int32_t, -16, 32)
+DEF_CONST (int32_t, -16, 64)
+DEF_CONST (int32_t, -16, 128)
+DEF_CONST (int32_t, -16, 256)
+DEF_CONST (int32_t, -16, 512)
+DEF_CONST (int32_t, -16, 1024)
+
+DEF_CONST (int64_t, -16, 2)
+DEF_CONST (int64_t, -16, 4)
+DEF_CONST (int64_t, -16, 8)
+DEF_CONST (int64_t, -16, 16)
+DEF_CONST (int64_t, -16, 32)
+DEF_CONST (int64_t, -16, 64)
+DEF_CONST (int64_t, -16, 128)
+DEF_CONST (int64_t, -16, 256)
+DEF_CONST (int64_t, -16, 512)
+
+/* { dg-final { scan-assembler-times {vmv\.v\.i\s+v[0-9]+,\s*-16} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
new file mode 100644
index 00000000000..99255ec5aa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_CONST (int16_t, 15, 2)
+DEF_CONST (int16_t, 15, 4)
+DEF_CONST (int16_t, 15, 8)
+DEF_CONST (int16_t, 15, 16)
+DEF_CONST (int16_t, 15, 32)
+DEF_CONST (int16_t, 15, 64)
+DEF_CONST (int16_t, 15, 128)
+DEF_CONST (int16_t, 15, 256)
+DEF_CONST (int16_t, 15, 512)
+DEF_CONST (int16_t, 15, 1024)
+DEF_CONST (int16_t, 15, 2048)
+
+DEF_CONST (int32_t, 15, 2)
+DEF_CONST (int32_t, 15, 4)
+DEF_CONST (int32_t, 15, 8)
+DEF_CONST (int32_t, 15, 16)
+DEF_CONST (int32_t, 15, 32)
+DEF_CONST (int32_t, 15, 64)
+DEF_CONST (int32_t, 15, 128)
+DEF_CONST (int32_t, 15, 256)
+DEF_CONST (int32_t, 15, 512)
+DEF_CONST (int32_t, 15, 1024)
+
+DEF_CONST (int64_t, 15, 2)
+DEF_CONST (int64_t, 15, 4)
+DEF_CONST (int64_t, 15, 8)
+DEF_CONST (int64_t, 15, 16)
+DEF_CONST (int64_t, 15, 32)
+DEF_CONST (int64_t, 15, 64)
+DEF_CONST (int64_t, 15, 128)
+DEF_CONST (int64_t, 15, 256)
+DEF_CONST (int64_t, 15, 512)
+
+/* { dg-final { scan-assembler-times {vmv\.v\.i\s+v[0-9]+,\s*15} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
new file mode 100644
index 00000000000..a9c8ae34ba7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_CONST (_Float16, 0, 2)
+DEF_CONST (_Float16, 0, 4)
+DEF_CONST (_Float16, 0, 8)
+DEF_CONST (_Float16, 0, 16)
+DEF_CONST (_Float16, 0, 32)
+DEF_CONST (_Float16, 0, 64)
+DEF_CONST (_Float16, 0, 128)
+DEF_CONST (_Float16, 0, 256)
+DEF_CONST (_Float16, 0, 512)
+DEF_CONST (_Float16, 0, 1024)
+DEF_CONST (_Float16, 0, 2048)
+
+DEF_CONST (float, 0, 2)
+DEF_CONST (float, 0, 4)
+DEF_CONST (float, 0, 8)
+DEF_CONST (float, 0, 16)
+DEF_CONST (float, 0, 32)
+DEF_CONST (float, 0, 64)
+DEF_CONST (float, 0, 128)
+DEF_CONST (float, 0, 256)
+DEF_CONST (float, 0, 512)
+DEF_CONST (float, 0, 1024)
+
+DEF_CONST (double, 0, 2)
+DEF_CONST (double, 0, 4)
+DEF_CONST (double, 0, 8)
+DEF_CONST (double, 0, 16)
+DEF_CONST (double, 0, 32)
+DEF_CONST (double, 0, 64)
+DEF_CONST (double, 0, 128)
+DEF_CONST (double, 0, 256)
+DEF_CONST (double, 0, 512)
+
+/* { dg-final { scan-assembler-times {vmv\.v\.i\s+v[0-9]+,\s*0} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
new file mode 100644
index 00000000000..50d1515aff6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_CONST (_Float16, 8.88, 2)
+DEF_CONST (_Float16, 8.88, 4)
+DEF_CONST (_Float16, 8.88, 8)
+DEF_CONST (_Float16, 8.88, 16)
+DEF_CONST (_Float16, 8.88, 32)
+DEF_CONST (_Float16, 8.88, 64)
+DEF_CONST (_Float16, 8.88, 128)
+DEF_CONST (_Float16, 8.88, 256)
+DEF_CONST (_Float16, 8.88, 512)
+DEF_CONST (_Float16, 8.88, 1024)
+DEF_CONST (_Float16, 8.88, 2048)
+
+DEF_CONST (float, 8.88, 2)
+DEF_CONST (float, 8.88, 4)
+DEF_CONST (float, 8.88, 8)
+DEF_CONST (float, 8.88, 16)
+DEF_CONST (float, 8.88, 32)
+DEF_CONST (float, 8.88, 64)
+DEF_CONST (float, 8.88, 128)
+DEF_CONST (float, 8.88, 256)
+DEF_CONST (float, 8.88, 512)
+DEF_CONST (float, 8.88, 1024)
+
+DEF_CONST (double, 8.88, 2)
+DEF_CONST (double, 8.88, 4)
+DEF_CONST (double, 8.88, 8)
+DEF_CONST (double, 8.88, 16)
+DEF_CONST (double, 8.88, 32)
+DEF_CONST (double, 8.88, 64)
+DEF_CONST (double, 8.88, 128)
+DEF_CONST (double, 8.88, 256)
+DEF_CONST (double, 8.88, 512)
+
+/* { dg-final { scan-assembler-times {vfmv\.v\.f\s+v[0-9]+,\s*[a-x0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
new file mode 100644
index 00000000000..afc2a877718
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_CONST (int16_t, 116, 2)
+DEF_CONST (int16_t, 116, 4)
+DEF_CONST (int16_t, 116, 8)
+DEF_CONST (int16_t, 116, 16)
+DEF_CONST (int16_t, 116, 32)
+DEF_CONST (int16_t, 116, 64)
+DEF_CONST (int16_t, 116, 128)
+DEF_CONST (int16_t, 116, 256)
+DEF_CONST (int16_t, 116, 512)
+DEF_CONST (int16_t, 116, 1024)
+DEF_CONST (int16_t, 116, 2048)
+
+DEF_CONST (int32_t, 116, 2)
+DEF_CONST (int32_t, 116, 4)
+DEF_CONST (int32_t, 116, 8)
+DEF_CONST (int32_t, 116, 16)
+DEF_CONST (int32_t, 116, 32)
+DEF_CONST (int32_t, 116, 64)
+DEF_CONST (int32_t, 116, 128)
+DEF_CONST (int32_t, 116, 256)
+DEF_CONST (int32_t, 116, 512)
+DEF_CONST (int32_t, 116, 1024)
+
+DEF_CONST (int64_t, 116, 2)
+DEF_CONST (int64_t, 116, 4)
+DEF_CONST (int64_t, 116, 8)
+DEF_CONST (int64_t, 116, 16)
+DEF_CONST (int64_t, 116, 32)
+DEF_CONST (int64_t, 116, 64)
+DEF_CONST (int64_t, 116, 128)
+DEF_CONST (int64_t, 116, 256)
+DEF_CONST (int64_t, 116, 512)
+
+/* { dg-final { scan-assembler-times {vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 2a5baef747b..00a8a8d2849 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -150,3 +150,17 @@ typedef double v512df __attribute__ ((vector_size (4096)));
     for (int i = 0; i < NUM; ++i)                                              \
       a[i] = OP b[i];                                                          \
   }
+
+#define DEF_CONST(TYPE, VAL, NUM)                                              \
+  void const_##TYPE##_##NUM (TYPE *restrict a)                                 \
+  {                                                                            \
+    for (int i = 0; i < NUM; ++i)                                              \
+      a[i] = VAL;                                                              \
+  }
+
+#define DEF_SERIES(TYPE, BASE, STEP, NUM, SUFFIX)                              \
+  void series_##TYPE##_##SUFFIX (TYPE *restrict a)                             \
+  {                                                                            \
+    for (TYPE i = 0; i < NUM; ++i)                                             \
+      a[i] = (BASE) + i * (STEP);                                              \
+  }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
new file mode 100644
index 00000000000..b575bb9e60b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_SERIES (int16_t, 0, 1, 2, b0s1n2)
+DEF_SERIES (int16_t, 0, 1, 4, b0s1n4)
+DEF_SERIES (int16_t, 0, 1, 8, b0s1n8)
+DEF_SERIES (int16_t, 0, 1, 16, b0s1n16)
+DEF_SERIES (int16_t, 0, 1, 32, b0s1n32)
+DEF_SERIES (int16_t, 0, 1, 64, b0s1n64)
+DEF_SERIES (int16_t, 0, 1, 128, b0s1n128)
+DEF_SERIES (int16_t, 0, 1, 256, b0s1n256)
+DEF_SERIES (int16_t, 0, 1, 512, b0s1n512)
+DEF_SERIES (int16_t, 0, 1, 1024, b0s1n1024)
+DEF_SERIES (int16_t, 0, 1, 2048, b0s1n2048)
+
+DEF_SERIES (int32_t, 0, 1, 2, b0s1n2)
+DEF_SERIES (int32_t, 0, 1, 4, b0s1n4)
+DEF_SERIES (int32_t, 0, 1, 8, b0s1n8)
+DEF_SERIES (int32_t, 0, 1, 16, b0s1n16)
+DEF_SERIES (int32_t, 0, 1, 32, b0s1n32)
+DEF_SERIES (int32_t, 0, 1, 64, b0s1n64)
+DEF_SERIES (int32_t, 0, 1, 128, b0s1n128)
+DEF_SERIES (int32_t, 0, 1, 256, b0s1n256)
+DEF_SERIES (int32_t, 0, 1, 512, b0s1n512)
+DEF_SERIES (int32_t, 0, 1, 1024, b0s1n1024)
+
+DEF_SERIES (int64_t, 0, 1, 2, b0s1n2)
+DEF_SERIES (int64_t, 0, 1, 4, b0s1n4)
+DEF_SERIES (int64_t, 0, 1, 8, b0s1n8)
+DEF_SERIES (int64_t, 0, 1, 16, b0s1n16)
+DEF_SERIES (int64_t, 0, 1, 32, b0s1n32)
+DEF_SERIES (int64_t, 0, 1, 64, b0s1n64)
+DEF_SERIES (int64_t, 0, 1, 128, b0s1n128)
+DEF_SERIES (int64_t, 0, 1, 256, b0s1n256)
+DEF_SERIES (int64_t, 0, 1, 512, b0s1n512)
+
+/* { dg-final { scan-assembler-times {vid\.v\s+v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
new file mode 100644
index 00000000000..c84eed158e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_SERIES (int16_t, 1, -1, 2, b1sm1n2)
+DEF_SERIES (int16_t, 3, -1, 4, b3sm1n4)
+DEF_SERIES (int16_t, 7, -1, 8, b7sm1n8)
+DEF_SERIES (int16_t, 15, -1, 16, b15sm1n16)
+DEF_SERIES (int16_t, 31, -1, 32, b31sm1n32)
+DEF_SERIES (int16_t, 63, -1, 64, b63sm1n64)
+DEF_SERIES (int16_t, 127, -1, 128, b127sm1n128)
+DEF_SERIES (int16_t, 255, -1, 256, b255sm1n256)
+DEF_SERIES (int16_t, 511, -1, 512, b511sm1n512)
+DEF_SERIES (int16_t, 1023, -1, 1024, b1023sm1n1024)
+DEF_SERIES (int16_t, 2047, -1, 2048, b2047sm1n2048)
+
+DEF_SERIES (int32_t, 1, -1, 2, b0sm1n2)
+DEF_SERIES (int32_t, 3, -1, 4, b0sm1n4)
+DEF_SERIES (int32_t, 7, -1, 8, b0sm1n8)
+DEF_SERIES (int32_t, 15, -1, 16, b0sm1n16)
+DEF_SERIES (int32_t, 31, -1, 32, b0sm1n32)
+DEF_SERIES (int32_t, 63, -1, 64, b0sm1n64)
+DEF_SERIES (int32_t, 127, -1, 128, b0sm1n128)
+DEF_SERIES (int32_t, 255, -1, 256, b0sm1n256)
+DEF_SERIES (int32_t, 511, -1, 512, b0sm1n512)
+DEF_SERIES (int32_t, 1023, -1, 1024, b0sm1n1024)
+
+DEF_SERIES (int64_t, 1, -1, 2, b0sm1n2)
+DEF_SERIES (int64_t, 3, -1, 4, b0sm1n4)
+DEF_SERIES (int64_t, 7, -1, 8, b0sm1n8)
+DEF_SERIES (int64_t, 15, -1, 16, b0sm1n16)
+DEF_SERIES (int64_t, 31, -1, 32, b0sm1n32)
+DEF_SERIES (int64_t, 63, -1, 64, b0sm1n64)
+DEF_SERIES (int64_t, 127, -1, 128, b0sm1n128)
+DEF_SERIES (int64_t, 255, -1, 256, b0sm1n256)
+DEF_SERIES (int64_t, 511, -1, 512, b0sm1n512)
+
+/* { dg-final { scan-assembler-times {vid\.v\s+v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
new file mode 100644
index 00000000000..16cce76dcf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_SERIES (int16_t, 0, 8, 2, b0s8n2)
+DEF_SERIES (int16_t, 0, 8, 4, b0s8n4)
+DEF_SERIES (int16_t, 0, 8, 8, b0s8n8)
+DEF_SERIES (int16_t, 0, 8, 16, b0s8n16)
+DEF_SERIES (int16_t, 0, 8, 32, b0s8n32)
+DEF_SERIES (int16_t, 0, 8, 64, b0s8n64)
+DEF_SERIES (int16_t, 0, 8, 128, b0s8n128)
+DEF_SERIES (int16_t, 0, 8, 256, b0s8n256)
+DEF_SERIES (int16_t, 0, 8, 512, b0s8n512)
+DEF_SERIES (int16_t, 0, 8, 1024, b0s8n1024)
+DEF_SERIES (int16_t, 0, 8, 2048, b0s8n2048)
+
+DEF_SERIES (int32_t, 0, 8, 2, b0s8n2)
+DEF_SERIES (int32_t, 0, 8, 4, b0s8n4)
+DEF_SERIES (int32_t, 0, 8, 8, b0s8n8)
+DEF_SERIES (int32_t, 0, 8, 16, b0s8n16)
+DEF_SERIES (int32_t, 0, 8, 32, b0s8n32)
+DEF_SERIES (int32_t, 0, 8, 64, b0s8n64)
+DEF_SERIES (int32_t, 0, 8, 128, b0s8n128)
+DEF_SERIES (int32_t, 0, 8, 256, b0s8n256)
+DEF_SERIES (int32_t, 0, 8, 512, b0s8n512)
+DEF_SERIES (int32_t, 0, 8, 1024, b0s8n1024)
+
+DEF_SERIES (int64_t, 0, 8, 2, b0s8n2)
+DEF_SERIES (int64_t, 0, 8, 4, b0s8n4)
+DEF_SERIES (int64_t, 0, 8, 8, b0s8n8)
+DEF_SERIES (int64_t, 0, 8, 16, b0s8n16)
+DEF_SERIES (int64_t, 0, 8, 32, b0s8n32)
+DEF_SERIES (int64_t, 0, 8, 64, b0s8n64)
+DEF_SERIES (int64_t, 0, 8, 128, b0s8n128)
+DEF_SERIES (int64_t, 0, 8, 256, b0s8n256)
+DEF_SERIES (int64_t, 0, 8, 512, b0s8n512)
+
+/* { dg-final { scan-assembler-times {vid\.v\s+v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
new file mode 100644
index 00000000000..966391e1f5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+
+#include "def.h"
+
+DEF_SERIES (int16_t, 67, 7, 2, b99s7n2)
+DEF_SERIES (int16_t, 67, 7, 4, b99s7n4)
+DEF_SERIES (int16_t, 67, 7, 8, b99s7n8)
+DEF_SERIES (int16_t, 67, 7, 16, b99s7n16)
+DEF_SERIES (int16_t, 67, 7, 32, b99s7n32)
+DEF_SERIES (int16_t, 67, 7, 64, b99s7n64)
+DEF_SERIES (int16_t, 67, 7, 128, b99s7n128)
+DEF_SERIES (int16_t, 67, 7, 256, b99s7n256)
+DEF_SERIES (int16_t, 67, 7, 512, b99s7n512)
+DEF_SERIES (int16_t, 67, 7, 1024, b99s7n1024)
+DEF_SERIES (int16_t, 67, 7, 2048, b99s7n2048)
+
+DEF_SERIES (int32_t, 76, 7, 2, b99s7n2)
+DEF_SERIES (int32_t, 76, 7, 4, b99s7n4)
+DEF_SERIES (int32_t, 76, 7, 8, b99s7n8)
+DEF_SERIES (int32_t, 76, 7, 16, b99s7n16)
+DEF_SERIES (int32_t, 76, 7, 32, b99s7n32)
+DEF_SERIES (int32_t, 76, 7, 64, b99s7n64)
+DEF_SERIES (int32_t, 76, 7, 128, b99s7n128)
+DEF_SERIES (int32_t, 76, 7, 256, b99s7n256)
+DEF_SERIES (int32_t, 76, 7, 512, b99s7n512)
+DEF_SERIES (int32_t, 76, 7, 1024, b99s7n1024)
+
+DEF_SERIES (int64_t, 99, 7, 2, b99s7n2)
+DEF_SERIES (int64_t, 99, 7, 4, b99s7n4)
+DEF_SERIES (int64_t, 99, 7, 8, b99s7n8)
+DEF_SERIES (int64_t, 99, 7, 16, b99s7n16)
+DEF_SERIES (int64_t, 99, 7, 32, b99s7n32)
+DEF_SERIES (int64_t, 99, 7, 64, b99s7n64)
+DEF_SERIES (int64_t, 99, 7, 128, b99s7n128)
+DEF_SERIES (int64_t, 99, 7, 256, b99s7n256)
+DEF_SERIES (int64_t, 99, 7, 512, b99s7n512)
+
+/* { dg-final { scan-assembler-times {vid\.v\s+v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
