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[8.43.85.97]) by mx.google.com with ESMTPS id c3-20020aa7c983000000b0052349404b09si348568edt.663.2023.08.08.00.14.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 00:14:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ZtwrjsQC; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2992D3858032 for ; Tue, 8 Aug 2023 07:14:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2992D3858032 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691478844; bh=WQhZsfiSXOgI9Ad3ElsrAb7/oBLV+5nDgqjNWc2K8a4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ZtwrjsQCtaCjq262SYM3prsrPZRYOgpS07N5yE3XNGgTOch3tc95eZsW5Q5YCfHVA modA9fgZCL0P4mXseUKye/2n24x4Cv87yh3ISInpnFPE8egQVqjDJd9Fu+ZxUcXCyI wXEhnm43BYJrpTETlLBiabv7JYXhE+pD9uymdWmQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 024083858D33 for ; Tue, 8 Aug 2023 07:13:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 024083858D33 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="434592293" X-IronPort-AV: E=Sophos;i="6.01,263,1684825200"; d="scan'208";a="434592293" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 00:13:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845345863" X-IronPort-AV: E=Sophos;i="6.01,263,1684825200"; d="scan'208";a="845345863" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 00:13:15 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7DA8B1005188; Tue, 8 Aug 2023 15:13:14 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 3/3] Emit a warning when AVX10 options conflict in vector width Date: Tue, 8 Aug 2023 15:13:12 +0800 Message-Id: <20230808071312.1569559-4-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230808071312.1569559-1-haochen.jiang@intel.com> References: <20230808071312.1569559-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773644137538394109 X-GMAIL-MSGID: 1773644137538394109 gcc/ChangeLog: * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10-max-512bit for -march=native. * common/config/i386/i386-common.cc (ix86_check_avx10_vector_width): New function to check isa_flags to emit a warning when there is a conflict in AVX10 options for vector width. (ix86_handle_option): Add check for avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-15.c: New test. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto. --- gcc/common/config/i386/i386-common.cc | 20 ++++++++++++++++++++ gcc/config/i386/driver-i386.cc | 3 ++- gcc/config/i386/i386-options.cc | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-15.c | 5 +++++ gcc/testsuite/gcc.target/i386/avx10_1-16.c | 5 +++++ gcc/testsuite/gcc.target/i386/avx10_1-17.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/avx10_1-18.c | 13 +++++++++++++ 7 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-15.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-16.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-17.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-18.c diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index ec94251dd4c..db88befc9b8 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -428,6 +428,24 @@ ix86_check_avx512 (struct gcc_options *opts) return true; } +/* Emit a warning when there is a conflict vector width in AVX10 options. */ +static void +ix86_check_avx10_vector_width (struct gcc_options *opts, bool avx10_max_512) +{ + if (avx10_max_512) + { + if (((opts->x_ix86_isa_flags2 | ~OPTION_MASK_ISA2_AVX10_512BIT) + == ~OPTION_MASK_ISA2_AVX10_512BIT) + && (opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_AVX10_512BIT)) + warning (0, "The options used for AVX10 have conflict vector width, " + "using the latter 512 as vector width"); + } + else if (opts->x_ix86_isa_flags2 & opts->x_ix86_isa_flags2_explicit + & OPTION_MASK_ISA2_AVX10_512BIT) + warning (0, "The options used for AVX10 have conflict vector width, " + "using the latter 256 as vector width"); +} + /* Implement TARGET_HANDLE_OPTION. */ bool @@ -1415,6 +1433,7 @@ ix86_handle_option (struct gcc_options *opts, return true; case OPT_mavx10_1_256: + ix86_check_avx10_vector_width (opts, false); opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET; opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_512BIT_SET; @@ -1424,6 +1443,7 @@ ix86_handle_option (struct gcc_options *opts, return true; case OPT_mavx10_1_512: + ix86_check_avx10_vector_width (opts, true); opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET; opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_512BIT_SET; diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 227ace6ff83..f4551a74e3a 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -854,7 +854,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) options = concat (options, " ", isa_names_table[i].option, NULL); } - else if (isa_names_table[i].feature != FEATURE_AVX10_1) + else if ((isa_names_table[i].feature != FEATURE_AVX10_1) + && (isa_names_table[i].feature != FEATURE_AVX10_512BIT)) options = concat (options, neg_option, isa_names_table[i].option + 2, NULL); } diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index b2281fbd4b5..8f9b825b527 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -985,7 +985,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], ix86_opt_ix86_no, ix86_opt_str, ix86_opt_enum, - ix86_opt_isa, + ix86_opt_isa }; static const struct diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c b/gcc/testsuite/gcc.target/i386/avx10_1-15.c new file mode 100644 index 00000000000..fd873c9694c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-15.c @@ -0,0 +1,5 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1-512 -mavx10.1-256" } */ +/* { dg-warning "The options used for AVX10 have conflict vector width, using the latter 256 as vector width" "" { target *-*-* } 0 } */ + +#include "avx10_1-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c b/gcc/testsuite/gcc.target/i386/avx10_1-16.c new file mode 100644 index 00000000000..1e664ebd1f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-16.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1-256 -mavx10.1-512" } */ +/* { dg-warning "The options used for AVX10 have conflict vector width, using the latter 512 as vector width" "" { target *-*-* } 0 } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c new file mode 100644 index 00000000000..7dfff3aeeac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-17.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +#include + +__attribute__ ((target ("avx10.1-512,avx10.1-256"))) void +f1 () +{ /* { dg-warning "The options used for AVX10 have conflict vector width, using the latter 256 as vector width" } */ + register __m256d a __asm ("ymm17"); + register __m256d b __asm ("ymm16"); + a = _mm256_add_pd (a, b); + asm volatile ("" : "+v" (a)); +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c b/gcc/testsuite/gcc.target/i386/avx10_1-18.c new file mode 100644 index 00000000000..955cca185fd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-18.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx10.1-256,avx10.1-512"))) __m512d +foo () +{ /* { dg-warning "The options used for AVX10 have conflict vector width, using the latter 512 as vector width" } */ + __m512d a, b; + a = a + b; + return a; +}