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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id jo5-20020a170906f6c500b00992fef5cff9si7029561ejb.497.2023.08.08.00.15.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 00:15:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=k8qBF2MP; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9BBE23855580 for ; Tue, 8 Aug 2023 07:15:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9BBE23855580 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691478901; bh=ncDd64/56y8pzHzFFk2+noLvAppfIWQOoqXu4RvsB24=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=k8qBF2MPzsICo1T6t94O1GMBCigvMxBNhBl4Krnha6F/bLm8zzXm4Na7r5PyHIHVq NsJ1uRX9vYXgFb0VFy33fcwn+UlracPCl1Rqf3qfBpnj2jZik/FF0AP/GbxSQmThPD wbEmJ/eBgC1a6SD397GXzbeSJlyyHQmJA8y5J0V0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 2A7473858C54 for ; Tue, 8 Aug 2023 07:13:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2A7473858C54 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="434592298" X-IronPort-AV: E=Sophos;i="6.01,263,1684825200"; d="scan'208";a="434592298" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 00:13:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845345867" X-IronPort-AV: E=Sophos;i="6.01,263,1684825200"; d="scan'208";a="845345867" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 00:13:15 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7AD5810054DE; Tue, 8 Aug 2023 15:13:14 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 2/3] Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 with AVX512 enabled Date: Tue, 8 Aug 2023 15:13:11 +0800 Message-Id: <20230808071312.1569559-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230808071312.1569559-1-haochen.jiang@intel.com> References: <20230808071312.1569559-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773644227300207328 X-GMAIL-MSGID: 1773644227300207328 gcc/ChangeLog: * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10.1 for -march=native. * config/i386/i386-options.cc (ix86_check_avx10): New function to check isa_flags and isa_flags_explicit to emit warning when AVX10 is enabled by "-m" option. (ix86_check_avx512): New function to check isa_flags and isa_flags_explicit to emit warning when AVX512 is enabled by "-m" option. (ix86_handle_option): Do not change the flags when warning is emitted. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-11.c: New test. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. --- gcc/common/config/i386/i386-common.cc | 68 +++++++++++++++++----- gcc/config/i386/driver-i386.cc | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-11.c | 5 ++ gcc/testsuite/gcc.target/i386/avx10_1-12.c | 13 +++++ gcc/testsuite/gcc.target/i386/avx10_1-13.c | 5 ++ gcc/testsuite/gcc.target/i386/avx10_1-14.c | 13 +++++ 6 files changed, 91 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-11.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-12.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-13.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-14.c diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 6c3bebb1846..ec94251dd4c 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -388,6 +388,46 @@ set_malign_value (const char **flag, unsigned value) *flag = r; } +/* Emit a warning when using -mno-avx512{f,vl,bw,dq,cd,bf16,fp16,vbmi,vbmi2, + vnni,ifma,bitalg,vpopcntdq} with -mavx10.1 and above. */ +static bool +ix86_check_avx10 (struct gcc_options *opts) +{ + if (opts->x_ix86_isa_flags2 & opts->x_ix86_isa_flags2_explicit + & OPTION_MASK_ISA2_AVX10_1) + { + warning (0, "%<-mno-avx512{f,vl,bw,dq,cd,bf16,fp16,vbmi,vbmi2,vnni,ifma," + "bitalg,vpopcntdq}%> are ignored with %<-mavx10.1%> and above"); + return false; + } + + return true; +} + +/* Emit a warning when using -mno-avx10.1 with -mavx512{f,vl,bw,dq,cd,bf16, + fp16,vbmi,vbmi2,vnni,ifma,bitalg,vpopcntdq}. */ +static bool +ix86_check_avx512 (struct gcc_options *opts) +{ + if ((opts->x_ix86_isa_flags & opts->x_ix86_isa_flags_explicit + & (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD + | OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512BW + | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512IFMA + | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI2 + | OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VPOPCNTDQ + | OPTION_MASK_ISA_AVX512BITALG)) + || (opts->x_ix86_isa_flags2 & opts->x_ix86_isa_flags2_explicit + & (OPTION_MASK_ISA2_AVX512FP16 | OPTION_MASK_ISA2_AVX512BF16))) + { + warning (0, "%<-mno-avx10.1%> is ignored when using with " + "%<-mavx512{f,vl,bw,dq,cd,bf16,fp16,vbmi,vbmi2,vnni," + "ifma,bitalg,vpopcntdq}%>"); + return false; + } + + return true; +} + /* Implement TARGET_HANDLE_OPTION. */ bool @@ -609,7 +649,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET; @@ -624,7 +664,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET; @@ -898,7 +938,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET; @@ -913,7 +953,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET; @@ -926,7 +966,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET; @@ -940,7 +980,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; opts->x_ix86_isa_flags_explicit @@ -954,7 +994,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET; opts->x_ix86_isa_flags_explicit @@ -970,7 +1010,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET; @@ -1037,7 +1077,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; @@ -1050,7 +1090,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; @@ -1065,7 +1105,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET; @@ -1078,7 +1118,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; @@ -1091,7 +1131,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET; } - else + else if (ix86_check_avx10 (opts)) { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; @@ -1367,7 +1407,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; } - else + else if (ix86_check_avx512 (opts)) { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET; diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 08d0aed6183..227ace6ff83 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -854,7 +854,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) options = concat (options, " ", isa_names_table[i].option, NULL); } - else + else if (isa_names_table[i].feature != FEATURE_AVX10_1) options = concat (options, neg_option, isa_names_table[i].option + 2, NULL); } diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c b/gcc/testsuite/gcc.target/i386/avx10_1-11.c new file mode 100644 index 00000000000..10c8d781dd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-11.c @@ -0,0 +1,5 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1 -mno-avx512f" } */ +/* { dg-warning "'-mno-avx512{f,vl,bw,dq,cd,bf16,fp16,vbmi,vbmi2,vnni,ifma,bitalg,vpopcntdq}' are ignored with '-mavx10.1' and above" "" { target *-*-* } 0 } */ + +#include "avx10_1-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c new file mode 100644 index 00000000000..b79c92ad002 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +#include + +__attribute__ ((target ("avx10.1,no-avx512f"))) void +f1 () +{ /* { dg-warning "'-mno-avx512{f,vl,bw,dq,cd,bf16,fp16,vbmi,vbmi2,vnni,ifma,bitalg,vpopcntdq}' are ignored with '-mavx10.1' and above" } */ + register __m256d a __asm ("ymm17"); + register __m256d b __asm ("ymm16"); + a = _mm256_add_pd (a, b); + asm volatile ("" : "+v" (a)); +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c new file mode 100644 index 00000000000..156d59f1d35 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c @@ -0,0 +1,5 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -mavx512f -mno-avx10.1" } */ +/* { dg-warning "'-mno-avx10.1' is ignored when using with '-mavx512{f,vl,bw,dq,cd,bf16,fp16,vbmi,vbmi2,vnni,ifma,bitalg,vpopcntdq}'" "" { target *-*-* } 0 } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c new file mode 100644 index 00000000000..23d2ba8bc64 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-14.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx512f,no-avx10.1"))) __m512d +foo () +{ /* { dg-warning "'-mno-avx10.1' is ignored when using with '-mavx512{f,vl,bw,dq,cd,bf16,fp16,vbmi,vbmi2,vnni,ifma,bitalg,vpopcntdq}'" } */ + __m512d a, b; + a = a + b; + return a; +}