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(unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 445AA40E10; Sun, 6 Aug 2023 12:51:17 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: Jiajie Chen Subject: [PATCH 8/9] LoongArch: Do not emit SF/DF <-> DI conversion in loongarch32 Date: Sun, 6 Aug 2023 20:50:05 +0800 Message-ID: <20230806125010.283900-8-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230806125010.283900-1-c@jia.je> References: <20230806125010.283900-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773484378486363209 X-GMAIL-MSGID: 1773484378486363209 In loongarch32 target, conversions between SF/DF and DI are not supported. gcc/ChangeLog: * config/loongarch/loongarch.md: Check TARGET_64BIT in insns regarding SF/DF <-> DI conversion. --- gcc/config/loongarch/loongarch.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index c611a8a822a..bced4b08569 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1504,7 +1504,7 @@ (define_insn "floatdidf2" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:DI 1 "register_operand" "f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" "ffint.d.l\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "DF") @@ -1522,7 +1522,7 @@ (define_insn "floatdisf2" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:DI 1 "register_operand" "f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" "ffint.s.l\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF") @@ -1576,7 +1576,7 @@ (define_expand "fixuns_truncdfdi2" [(set (match_operand:DI 0 "register_operand") (unsigned_fix:DI (match_operand:DF 1 "register_operand")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" { rtx reg1 = gen_reg_rtx (DFmode); rtx reg2 = gen_reg_rtx (DFmode); @@ -1658,7 +1658,7 @@ (define_expand "fixuns_truncsfdi2" [(set (match_operand:DI 0 "register_operand") (unsigned_fix:DI (match_operand:SF 1 "register_operand")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" { rtx reg1 = gen_reg_rtx (SFmode); rtx reg2 = gen_reg_rtx (SFmode);