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(unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id A49BF41D82; Sun, 6 Aug 2023 12:51:10 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: Jiajie Chen Subject: [PATCH 3/9] LoongArch: Fix SI division for loongarch32 target Date: Sun, 6 Aug 2023 20:50:00 +0800 Message-ID: <20230806125010.283900-3-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230806125010.283900-1-c@jia.je> References: <20230806125010.283900-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-14.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773484239202146089 X-GMAIL-MSGID: 1773484239202146089 Add TARGET_64BIT check for loongarch64-only handling of SI division. It shall not promote SI to DI before division in loongarch32 target. gcc/ChangeLog: * config/loongarch/loongarch.md: Add TARGET_64BIT check for loongarch64-only handling of SI division. --- gcc/config/loongarch/loongarch.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index b37e070660f..95c5b25d22a 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -851,7 +851,7 @@ (match_operand:GPR 2 "register_operand")))] "" { - if (GET_MODE (operands[0]) == SImode) + if (GET_MODE (operands[0]) == SImode && TARGET_64BIT) { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode);