diff mbox series

[2/9] LoongArch: Fix default ISA setting

Message ID 20230806125010.283900-2-c@jia.je
State Unresolved
Headers
Series [1/9] LoongArch: Introduce loongarch32 target |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Jiajie Chen Aug. 6, 2023, 12:49 p.m. UTC 
  When loongarch_arch_target is called, la_target has not been
initialized, thus the macro LARCH_ACTUAL_ARCH always equals to zero.

This commit fixes by expanding the macro and reading the latest value.
It permits -march=loongarch64 when the default target is loongarch32 and
vice versa.

gcc/ChangeLog:

	* config/loongarch/loongarch-opts.cc (loongarch_config_target):
	  Fix -march detection.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/arch-1.c: New test.
	* gcc.target/loongarch/arch-2.c: New test.
	* gcc.target/loongarch/arch-3.c: New test.
---
 gcc/config/loongarch/loongarch-opts.cc      | 5 ++++-
 gcc/testsuite/gcc.target/loongarch/arch-1.c | 5 +++++
 gcc/testsuite/gcc.target/loongarch/arch-2.c | 5 +++++
 gcc/testsuite/gcc.target/loongarch/arch-3.c | 6 ++++++
 4 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-3.c

Comments

Xi Ruoyao Aug. 9, 2023, 3:38 a.m. UTC | #1 
On Sun, 2023-08-06 at 20:49 +0800, Jiajie Chen via Gcc-patches wrote:
> When loongarch_arch_target is called, la_target has not been
> initialized, thus the macro LARCH_ACTUAL_ARCH always equals to zero.
> 
> This commit fixes by expanding the macro and reading the latest value.
> It permits -march=loongarch64 when the default target is loongarch32 and
> vice versa.
> 
> gcc/ChangeLog:
> 
>         * config/loongarch/loongarch-opts.cc (loongarch_config_target):
>           Fix -march detection.

Nit: the first letter 'F' of the second line should align with '*' of
the first line, not 'c'.

/* snip */

> diff --git a/gcc/testsuite/gcc.target/loongarch/arch-3.c b/gcc/testsuite/gcc.target/loongarch/arch-3.c
> new file mode 100644
> index 00000000000..543b93883bd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/arch-3.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=loongarch64 -mabi=ilp32d" } */
> +int foo()
> +{
> +}
> +/* { dg-error "unable to implement ABI 'ilp32d' with instruction set 'la64/fpu64'" "" { target *-*-* } 0 } */

This is just wrong.  It's absolutely possible to implement ilp32d with
la64/fpu64.  LoongArch *.w instructions are always 32-bit operations, no
matter on LA32 or LA64.  They are different from RISC-V where many
instructions operate on 32-bit integers on RV32 but 64-bit integers on
RV64.

If you don't want to spend your time to implement it you should use
`sorry ("%<-mabi=ilp32d%> is not implemented for la64");` instead.

Yes, I know there is some (mis)uses of TARGET_64BIT in the
config/loongarch code where TARGET_ABI_LP64 should be actually used
instead.  They are bugs preventing us from implementing -mabi=ilp32d -
march=loongarch64 and they should be fixed.  They are not our excuse to
blindly "simulate" what RISC-V has.
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index 9fc0bbbcb6e..29c0c4468bb 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -246,7 +246,10 @@  loongarch_config_target (struct loongarch_target *target,
 config_target_isa:
 
   /* Get default ISA from "-march" or its default value.  */
-  t.isa = loongarch_cpu_default_isa[LARCH_ACTUAL_ARCH];
+  if (t.cpu_arch == TARGET_ARCH_NATIVE)
+    t.isa = loongarch_cpu_default_isa[t.cpu_native];
+  else
+    t.isa = loongarch_cpu_default_isa[t.cpu_arch];
 
   /* Apply incremental changes.  */
   /* "-march=native" overrides the default FPU type.  */
diff --git a/gcc/testsuite/gcc.target/loongarch/arch-1.c b/gcc/testsuite/gcc.target/loongarch/arch-1.c
new file mode 100644
index 00000000000..379036ec76f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/arch-1.c
@@ -0,0 +1,5 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/arch-2.c b/gcc/testsuite/gcc.target/loongarch/arch-2.c
new file mode 100644
index 00000000000..55d646902a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/arch-2.c
@@ -0,0 +1,5 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch32 -mabi=ilp32d" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/arch-3.c b/gcc/testsuite/gcc.target/loongarch/arch-3.c
new file mode 100644
index 00000000000..543b93883bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/arch-3.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=ilp32d" } */
+int foo()
+{
+}
+/* { dg-error "unable to implement ABI 'ilp32d' with instruction set 'la64/fpu64'" "" { target *-*-* } 0 } */